Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753674Ab3HDJsD (ORCPT ); Sun, 4 Aug 2013 05:48:03 -0400 Received: from up.free-electrons.com ([94.23.35.102]:36994 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753568Ab3HDJr7 (ORCPT ); Sun, 4 Aug 2013 05:47:59 -0400 From: Maxime Ripard To: linux-arm-kernel@lists.infradead.org Cc: Emilio Lopez , kevin.z.m.zh@gmail.com, sunny@allwinnertech.com, shuge@allwinnertech.com, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Maxime Ripard Subject: [PATCHv3 05/10] ARM: sunxi: Add Allwinner A31 DTSI Date: Sun, 4 Aug 2013 11:47:32 +0200 Message-Id: <1375609657-15434-6-git-send-email-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 1.8.3.4 In-Reply-To: <1375609657-15434-1-git-send-email-maxime.ripard@free-electrons.com> References: <1375609657-15434-1-git-send-email-maxime.ripard@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3970 Lines: 179 The Allwinner A31 SoC is a multimedia SoC powered by 4 Cortex-A7 and a PowerVR GPU. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 156 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 156 insertions(+) create mode 100644 arch/arm/boot/dts/sun6i-a31.dtsi diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi new file mode 100644 index 0000000..45487e4 --- /dev/null +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -0,0 +1,156 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + }; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc@01c00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + timer@01c20c00 { + compatible = "allwinner,sun4i-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = <0 18 1>, + <0 19 1>, + <0 20 1>, + <0 21 1>, + <0 22 1>; + clocks = <&osc>; + }; + + wdt1: watchdog@01c20ca0 { + compatible = "allwinner,sun6i-wdt"; + reg = <0x01c20ca0 0x20>; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <0 0 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <0 1 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <0 2 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <0 3 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + uart4: serial@01c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = <0 4 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + uart5: serial@01c29400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29400 0x400>; + interrupts = <0 5 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <1 9 0xf04>; + }; + }; +}; -- 1.8.3.4 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/