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Date: Mon, 12 Aug 2013 13:04:38 -0500
From: Felipe Balbi <balbi@ti.com>
To: Kumar Gala <galak@codeaurora.org>
CC: "Ivan T. Ivanov" <iivanov@mm-sol.com>, <balbi@ti.com>,
        <rob.herring@calxeda.com>, <pawel.moll@arm.com>,
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        <idos@codeaurora.org>, <mgautam@codeaurora.org>,
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        <linux-kernel@vger.kernel.org>, <linux-usb@vger.kernel.org>,
        <linux-omap@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>
Subject: Re: [RFC PATCH v2 1/3] usb: dwc3: msm: Add device tree binding
 information
Message-ID: <20130812180438.GC27954@radagast>
Reply-To: <balbi@ti.com>
References: <1376042027-9798-1-git-send-email-iivanov@mm-sol.com>
 <1376042027-9798-2-git-send-email-iivanov@mm-sol.com>
 <169628C9-00BA-4E58-BF65-7B180E6BE4ED@codeaurora.org>
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On Fri, Aug 09, 2013 at 10:31:58AM -0500, Kumar Gala wrote:
>=20
> On Aug 9, 2013, at 4:53 AM, Ivan T. Ivanov wrote:
>=20
> > From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
> >=20
> > MSM USB3.0 core wrapper consist of USB3.0 IP (SNPS)
>=20
> probably good to spell out Synopsys rather than SNPS

Synopsys (the company) has always used snps in their bindings though.

> > +Required properities :
> > +- compatible : sould be "qcom,dwc3-hsphy";
> > +- reg : offset and length of the register set in the memory map
> > +- clocks : phandles to clock instances of the device tree nodes
> > +- clock-names :
> > +	"xo" : External reference clock 19 MHz
> > +	"sleep_a_clk" : Sleep clock, used when USB3 core goes into low
> > +	power mode (U3).
> > +<supply-name>-supply : phandle to the regulator device tree node
> > +Required "supply-name" are:
> > +	"v1p8" : 1.8v supply for HSPHY
> > +	"v3p3" : 3.3v supply for HSPHY
> > +	"vbus" : vbus supply for host mode
> > +	"vddcx" : vdd supply for HS-PHY digital circuit operation

I believe these regulators belong to the PHY, not DWC3. Please write a
PHY driver.

> > +Required properities :
> > +- compatible : sould be "qcom,dwc3-ssphy";
> > +- reg : offset and length of the register set in the memory map
> > +- clocks : phandles to clock instances of the device tree nodes
> > +- clock-names :
> > +	"xo" : External reference clock 19 MHz
> > +	"ref_clk" : Reference clock - used in host mode.
> > +<supply-name>-supply : phandle to the regulator device tree node
> > +Required "supply-name" are:
> > +	"v1p8" : 1.8v supply for SS-PHY
> > +	"vddcx" : vdd supply for SS-PHY digital circuit operation

likewise, these regulators should be moved to the PHY driver.

> > +Required properties :
> > +- compatible : should be "qcom,dwc3"
> > +- reg : offset and length of the register set in the memory map
> > +	offset and length of the TCSR register for routing USB
> > +	signals to either picoPHY0 or picoPHY1.
> > +- clocks : phandles to clock instances of the device tree nodes
> > +- clock-names :
> > +	"core_clk" : Master/Core clock, have to be >=3D 125 MHz for SS
> > +	operation and >=3D 60MHz for HS operation
> > +	"iface_clk" : System bus AXI clock
> > +	"sleep_clk" : Sleep clock, used when USB3 core goes into low
> > +	power mode (U3).
> > +	"utmi_clk" : Generated by HS-PHY. Used to clock the low power
> > +	parts of thr HS Link layer.
> > +
> > +Optional properties :
> > +- gdsc-supply : phandle to the globally distributed switch controller
> > +  regulator node to the USB controller.
> > +
> > +Sub nodes:
> > +- Sub node for "DWC3 USB3 controller".
> > +  This sub node is required property for device node. The properties
> > +  of this subnode are specified in dwc3.txt.
>=20
> Is tx-fifo-resize required for qcom,dwc3? if so we should call that
> out in the binding.

AFAICT that's only needed for OMAP5 ES1.0. Unless Qualcomm also screwed
up default TX FIFO sizes :-p

--=20
balbi

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