Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753946Ab3HPNQ0 (ORCPT ); Fri, 16 Aug 2013 09:16:26 -0400 Received: from mail-oa0-f41.google.com ([209.85.219.41]:64882 "EHLO mail-oa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752948Ab3HPNQU (ORCPT ); Fri, 16 Aug 2013 09:16:20 -0400 MIME-Version: 1.0 In-Reply-To: <1375133350-18828-3-git-send-email-ddaney.cavm@gmail.com> References: <1375133350-18828-1-git-send-email-ddaney.cavm@gmail.com> <1375133350-18828-3-git-send-email-ddaney.cavm@gmail.com> Date: Fri, 16 Aug 2013 15:16:20 +0200 Message-ID: Subject: Re: [PATCH v2 2/2] gpio MIPS/OCTEON: Add a driver for OCTEON's on-chip GPIO pins. From: Linus Walleij To: David Daney Cc: Ralf Baechle , "linux-gpio@vger.kernel.org" , linux-mips@linux-mips.org, "linux-kernel@vger.kernel.org" , David Daney Content-Type: text/plain; charset=ISO-8859-1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 928 Lines: 27 On Mon, Jul 29, 2013 at 11:29 PM, David Daney wrote: > From: David Daney > > The SOCs in the OCTEON family have 16 (or in some cases 20) on-chip > GPIO pins, this driver handles them all. Configuring the pins as > interrupt sources is handled elsewhere (OCTEON's irq handling code). > > Signed-off-by: David Daney > --- > > Device tree binding defintions already exist for this device in > Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt I like this. Reviewed-by: Linus Walleij I guess you will merge both patches through the MIPS arch tree? Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/