Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751274Ab3HSJQ4 (ORCPT ); Mon, 19 Aug 2013 05:16:56 -0400 Received: from mail-oa0-f50.google.com ([209.85.219.50]:54958 "EHLO mail-oa0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751019Ab3HSJQz (ORCPT ); Mon, 19 Aug 2013 05:16:55 -0400 MIME-Version: 1.0 In-Reply-To: <20130815135314.GE19750@two.firstfloor.org> References: <1376411952-16718-1-git-send-email-jolsa@redhat.com> <1376411952-16718-2-git-send-email-jolsa@redhat.com> <20130815114040.GR24092@twins.programming.kicks-ass.net> <20130815135314.GE19750@two.firstfloor.org> Date: Mon, 19 Aug 2013 11:16:54 +0200 Message-ID: Subject: Re: [PATCH 1/2] perf x86: Make intel_pmu_enable_all to enable only active events From: Stephane Eranian To: Andi Kleen Cc: Peter Zijlstra , Jiri Olsa , LKML , Corey Ashford , Frederic Weisbecker , Paul Mackerras , Ingo Molnar , Arnaldo Carvalho de Melo Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 794 Lines: 17 On Thu, Aug 15, 2013 at 3:53 PM, Andi Kleen wrote: >> >> I think its a NOP; this is the global ctrl register but >> intel_pmu_disable_event() writes PERFEVTSELx.EN = 0, so even if you >> enable it in the global mask, the event should still be disabled. > > Yes the hardware ANDs the various enable bits in the different > registers. > Andi is correct. There is a logical AND between GLOBAL_CTRL and the individual PERFEVTCTL.EN bits. If the EN bit is zero, then the counter does not count. That also applies to fixed counters. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/