Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753776Ab3HVHce (ORCPT ); Thu, 22 Aug 2013 03:32:34 -0400 Received: from mail-db9lp0253.outbound.messaging.microsoft.com ([213.199.154.253]:25313 "EHLO db9outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753195Ab3HVHcb convert rfc822-to-8bit (ORCPT ); Thu, 22 Aug 2013 03:32:31 -0400 X-Forefront-Antispam-Report: CIP:70.37.183.190;KIP:(null);UIP:(null);IPV:NLI;H:mail.freescale.net;RD:none;EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zz1432Izz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzzz2dh2a8h839h8e2h8e3h944hd25hf0ah1220h1288h12a5h12a9h12bdh137ah13b6h1441h1504h1537h153bh15d0h162dh1631h1758h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1fe8h1ff5hbe9i1155h) From: Xiubo Li-B47053 To: Sascha Hauer CC: Tomasz Figa , Guo Shawn-R65073 , "thierry.reding@gmail.com" , "grant.likely@linaro.org" , "linux@arm.linux.org.uk" , "rob@landley.net" , "ian.campbell@citrix.com" , "swarren@wwwdotorg.org" , "mark.rutland@arm.com" , "pawel.moll@arm.com" , "rob.herring@calxeda.com" , "linux-arm-kernel@lists.infradead.org" , "linux-pwm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-doc@vger.kernel.org" , "linus.walleij@linaro.org" Subject: RE: [PATCH 4/4] Documentation: Add device tree bindings for Freescale FTM PWM Thread-Topic: [PATCH 4/4] Documentation: Add device tree bindings for Freescale FTM PWM Thread-Index: AQHOnhwezjS9uM7qaEqpBdTwwEdnOZmgDXMAgABm0CCAAFCAAIAADBjQ Date: Thu, 22 Aug 2013 07:32:25 +0000 Message-ID: <1DD289F6464F0949A2FCA5AA6DC23F827D241A@039-SN2MPN1-013.039d.mgd.msft.net> References: <1377054462-6283-1-git-send-email-Li.Xiubo@freescale.com> <1377054462-6283-5-git-send-email-Li.Xiubo@freescale.com> <1473340.OXSHEp7d4P@flatron> <1DD289F6464F0949A2FCA5AA6DC23F827D2244@039-SN2MPN1-013.039d.mgd.msft.net> <20130822062610.GR31036@pengutronix.de> In-Reply-To: <20130822062610.GR31036@pengutronix.de> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.192.208.56] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1160 Lines: 35 Hi Sascha, > > > Could you explain meaning of this property more precisely? I'm > > > interested especially how is this related to the PWM IP block and > boards. > > > > > > > Yes. > > There are 8 channels most. While the pinctrls of 4th and 5th channels > > could be used by uart's Rx and Tx, then these 2 channels won't be used > > for pwm output, so there will be 6 channels available by the pwm. > > Thus, the pwm chip will register only 6 pwms(6 channels) > > most("fsl,pwm-channel-orders = {0 1 2 3 6 7}").And also the "fsl,pwm- > > channel-number" will be 6. > > If the chip has eight PWMs I would register all of them. If some of them > are not routed out by the pinmux then just nothing happens if you use > them. In a sane devicetree they won't be referenced anyway when they are > not routed out of the SoC. > Yes, that's perfect well. I will do it in v2. Thanks very much. -- Best Regards, Xiubo -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/