Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753002Ab3I0QE0 (ORCPT ); Fri, 27 Sep 2013 12:04:26 -0400 Received: from e34.co.us.ibm.com ([32.97.110.152]:38474 "EHLO e34.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752266Ab3I0QEU (ORCPT ); Fri, 27 Sep 2013 12:04:20 -0400 Date: Fri, 27 Sep 2013 09:04:06 -0700 From: "Paul E. McKenney" To: Peter Zijlstra Cc: Joe Perches , Ingo Molnar , Tim Chen , Jason Low , Davidlohr Bueso , Ingo Molnar , Andrew Morton , Andrea Arcangeli , Alex Shi , Andi Kleen , Michel Lespinasse , Davidlohr Bueso , Matthew R Wilcox , Dave Hansen , Rik van Riel , Peter Hurley , linux-kernel@vger.kernel.org, linux-mm , tony.luck@intel.com, fenghua.yu@intel.com, linux-ia64@vger.kernel.org Subject: Re: [PATCH] checkpatch: Make the memory barrier test noisier Message-ID: <20130927160406.GY9093@linux.vnet.ibm.com> Reply-To: paulmck@linux.vnet.ibm.com References: <20130927060213.GA6673@gmail.com> <20130927112323.GJ3657@laptop.programming.kicks-ass.net> <1380289495.17366.91.camel@joe-AO722> <20130927134802.GA15690@laptop.programming.kicks-ass.net> <1380291257.17366.103.camel@joe-AO722> <20130927142605.GC15690@laptop.programming.kicks-ass.net> <1380292495.17366.106.camel@joe-AO722> <20130927145007.GD15690@laptop.programming.kicks-ass.net> <20130927151749.GA2149@linux.vnet.ibm.com> <20130927153434.GG15690@laptop.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20130927153434.GG15690@laptop.programming.kicks-ass.net> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-MML: No X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13092716-1542-0000-0000-000001CE3397 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1947 Lines: 41 On Fri, Sep 27, 2013 at 05:34:34PM +0200, Peter Zijlstra wrote: > On Fri, Sep 27, 2013 at 08:17:50AM -0700, Paul E. McKenney wrote: > > > Barriers are fundamentally about order; and order only makes sense if > > > there's more than 1 party to the game. > > > > Oddly enough, there is one exception that proves the rule... On Itanium, > > suppose we have the following code, with x initially equal to zero: > > > > CPU 1: ACCESS_ONCE(x) = 1; > > > > CPU 2: r1 = ACCESS_ONCE(x); r2 = ACCESS_ONCE(x); > > > > Itanium architects have told me that it really is possible for CPU 2 to > > see r1==1 and r2==0. Placing a memory barrier between CPU 2's pair of > > fetches prevents this, but without any other memory barrier to pair with. > > Oh man.. its really past time to sink that itanic already. > > I suppose it allows the cpu to reorder the reads in its pipeline and the > memory barrier disallows this. Curious.. does our memory-barriers.txt > file mention this 'fun' fact? Probably not. I was recently reminded of it by some people on the C++ standards committee. I had first heard of it about 5 years ago, but hadn't heard definitively until quite recently. I defer to the Itanium maintainers to actually make the required changes, should they choose to do so. I suppose that one way to handle it in the Linux kernel would be to make ACCESS_ONCE() be architecture specific, with Itanium placing a memory barrier either before or after --- either would work. But since Itanium seems to run Linux reliably, I am guessing that the probability of misordering is quite low. But again, the ball is firmly in the Itanium maintainers' courts, and I have added them on CC. Thanx, Paul -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/