Message-ID: <5245E6DB.4000401@tilera.com>
Date: Fri, 27 Sep 2013 16:13:15 -0400
From: Chris Metcalf <cmetcalf@tilera.com>
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To: Will Deacon <will.deacon@arm.com>
CC: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Tejun Heo <tj@kernel.org>, Christoph Lameter <cl@linux-foundation.org>,
        Benjamin Herrenschmidt <benh@kernel.crashing.org>,
        "rob.herring@calxeda.com" <rob.herring@calxeda.com>,
        Nicolas Pitre <nico@linaro.org>,
        Linus Torvalds <torvalds@linux-foundation.org>
Subject: Re: [PATCH] tile: use a more conservative __my_cpu_offset in CONFIG_PREEMPT
References: <201309261738.r8QHcGZX007708@farm-0012.internal.tilera.com> <20130926175754.GD7146@mudshark.cambridge.arm.com>
In-Reply-To: <20130926175754.GD7146@mudshark.cambridge.arm.com>
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On 9/26/2013 1:57 PM, Will Deacon wrote:
> Hi Chris,
>
> On Thu, Sep 26, 2013 at 06:24:53PM +0100, Chris Metcalf wrote:
>> [...]
>> +static inline unsigned long __my_cpu_offset(void)
>> +{
>> +	unsigned long tp;
>> +	register unsigned long *sp asm("sp");
>> +	asm("move %0, tp" : "=r" (tp) : "m" (*sp));
>> +	return tp;
>> +}
> Hehe, nice to see this hack working out for you too. One thing to check is
> whether you have any funky addressing modes (things like writeback or
> post-increment), since the "m" constraint can bite you if you don't actually
> use it in the asm.

Well, we do have post increments, though I don't see why this is a problem here.
We define a target specific constraint "U" that excludes post-increments, but
again I don't see why "m" would cause trouble here.  What was your experience?

-- 
Chris Metcalf, Tilera Corp.
http://www.tilera.com

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