Message-ID: <1380910065.2081.117.camel@joe-AO722>
Subject: Re: [PATCH v2 6/6] Introduce Intel RAPL power capping driver
From: Joe Perches <joe@perches.com>
To: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
        gregkh@linuxfoundation.org, len.brown@intel.com, rjw@sisk.pl,
        arjan@linux.intel.com, jacob.jun.pan@linux.intel.com
Date: Fri, 04 Oct 2013 11:07:45 -0700
In-Reply-To: <1380904616-17519-7-git-send-email-srinivas.pandruvada@linux.intel.com>
References: <1380904616-17519-1-git-send-email-srinivas.pandruvada@linux.intel.com>
	 <1380904616-17519-7-git-send-email-srinivas.pandruvada@linux.intel.com>
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On Fri, 2013-10-04 at 09:36 -0700, Srinivas Pandruvada wrote:
> The Intel Running Average Power Limit(RAPL) technology provides platform
> software with the ability to monitor, control, and get notifications on
> power usage.
[]
> diff --git a/drivers/powercap/Makefile b/drivers/powercap/Makefile
[]
> +/* bitmasks for RAPL MSRs, used by primitive access functions */
> +#define ENERGY_STATUS_MASK      0xffffffff
> +
> +#define POWER_LIMIT1_MASK       0x7FFF
> +#define POWER_LIMIT1_ENABLE     BIT(15)
> +#define POWER_LIMIT1_CLAMP      BIT(16)
> +
> +#define POWER_LIMIT2_MASK       (0x7FFFULL<<32)
> +#define POWER_LIMIT2_ENABLE     BIT_ULL(47)
> +#define POWER_LIMIT2_CLAMP      BIT_ULL(48)
> +#define POWER_PACKAGE_LOCK      BIT_ULL(63)
> +#define POWER_PP_LOCK           BIT(31)
> +
> +#define TIME_WINDOW1_MASK       (0x7F<<17)
> +#define TIME_WINDOW2_MASK       (0x7FULL<<49)


Is there a reason why these masks aren't all ULL?


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