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From: Daniel Phillips <phillips@arcor.de>
To: "Nakajima, Jun" <jun.nakajima@intel.com>, Jeff Garzik <jgarzik@pobox.com>,
       Robert Love <rml@tech9.net>
Subject: Re: [PATCH] hyper-threading information in /proc/cpuinfo
Date: Sat, 26 Oct 2002 01:51:25 +0200
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Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>,
       "Nakajima, Jun" <jun.nakajima@intel.com>,
       "'Dave Jones'" <davej@codemonkey.org.uk>,
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       "'Martin J. Bligh'" <mbligh@aracnet.com>
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On Saturday 26 October 2002 00:42, Nakajima, Jun wrote:
> The notion of "SMT (Simultaneous Multi-Threaded)" architecture has been
> there for a while (at least 8 years, as far as I know). You would get tons
> of info if you search it in Internet. 

Actually, what we were referring to is multiple complete, separate
processor cores on one chip.  Two complete cores turns in true 2X
performance, modulo cache effects, vs SMT which turns in anywhere
from 0 to 20% improvement.

MIPS does 2X processors/chip, and IBM is planning to do 32X.  I've
heard rumours of 128X as well.

-- 
Daniel
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