Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755170Ab3J3UZr (ORCPT ); Wed, 30 Oct 2013 16:25:47 -0400 Received: from smtp.codeaurora.org ([198.145.11.231]:55852 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755060Ab3J3UZm (ORCPT ); Wed, 30 Oct 2013 16:25:42 -0400 From: Stephen Boyd To: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland , Kumar Gala , Subject: [PATCH v2 4/6] edac: Document Krait L1/L2 EDAC driver binding Date: Wed, 30 Oct 2013 13:25:34 -0700 Message-Id: <1383164736-1849-5-git-send-email-sboyd@codeaurora.org> X-Mailer: git-send-email 1.8.4.2.564.g0d6cf24 In-Reply-To: <1383164736-1849-1-git-send-email-sboyd@codeaurora.org> References: <1383164736-1849-1-git-send-email-sboyd@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2222 Lines: 85 The Krait L1/L2 error reporting device is made up of two interrupts, one per-CPU interrupt for the L1 caches and one interrupt for the L2 cache. Cc: Mark Rutland Cc: Kumar Gala Cc: Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/arm/cpus.txt | 49 ++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index f32494d..0f7b27f 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -44,6 +44,8 @@ For the ARM architecture every CPU node must contain the following properties: "marvell,mohawk" "marvell,xsc3" "marvell,xscale" + "qcom,scorpion" + "qcom,krait" Example: @@ -75,3 +77,50 @@ Example: reg = <0x101>; }; }; + +If the compatible string contains "qcom,krait" there shall be an interrupts +property containing the L1/CPU error interrupt number. There shall also be an +l2-cache node containing the following properties: + + - compatible: Shall contain at least "cache" + - cache-level: Must be 2 + - interrupts: Shall contain the L2 error interrupt + +Example: + + cpus { + #address-cells = <1>; + #size-cells = <0>; + interrupts = <1 9 0xf04>; + compatible = "qcom,krait"; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + interrupts = <0 2 0x4>; + }; + }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/