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Date: Thu, 31 Oct 2002 13:57:24 +0100
From: Roger Luethi <rl@hellgate.ch>
To: "H.Rosmanith (Kernel Mailing List)" <kernel@wildsau.idv.uni.linz.at>
Cc: alan@lxorguk.ukuu.org.uk, sergeyssv@mail.ru, linux-kernel@vger.kernel.org
Subject: Re: VIA EPIA problem
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On Thu, 31 Oct 2002 12:36:20 +0100, H.Rosmanith (Kernel Mailing List) wrote:
> > 
> > My favorite suspect is currently byte 84 bit 3 in the configuration
> > registers. It does not exist in VT86C100A (which would explain why it's not
> > handled in Donald Becker's original code). According to VT6102 specs, it
> > indicates an error condition, according to VT6105 specs, it is reserved and
> > always reads 0.
> 
> okay, let's reopen the case. you want me to monitor this bit? perhaps

Bit 3 in 0x84 and 0x86 are those I'm most interested in. If the chip has
0x86 bit 3 cleared, try with having it set.

If that doesn't yield anything, you may want to monitor bytes 0x08, 0x09,
0x0c, 0x0d, 0x80, 0x81, 0x84 and 0x86. Just in case.

> it will be 1 in case of an error condition. for the via epia board, this
> would contradict with the specs, right? but *maybe* the bit is indeed

What spec? It seems okay with the one I have.

> 1 in case of an error, so we could possibly fix the problem just in time,
> instead of (ugly) storing some temporary value globally across functions.

That bit is just the obvious candidate, there might be others. Here's
hoping that Rhine chips don't turn off the TxEngine without setting a flag
to inform the driver.

Roger
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