From: Arnd Bergmann <arnd@arndb.de>
To: linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/4] ARM: STi: add stid127 soc support
Date: Thu, 30 Jan 2014 19:39:08 +0100
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Cc: devicetree@vger.kernel.org, Russell King <linux@arm.linux.org.uk>,
        kernel@stlinux.com, Srinivas Kandagatla <srinivas.kandagatla@st.com>,
        Linus Walleij <linus.walleij@linaro.org>,
        Patrice CHOTARD <patrice.chotard@st.com>, linux-kernel@vger.kernel.org,
        Stuart Menefy <stuart.menefy@st.com>, Rob Herring <robh+dt@kernel.org>,
        Grant Likely <grant.likely@linaro.org>,
        Giuseppe Cavallaro <peppe.cavallaro@st.com>, maxime.coquelin@st.com,
        alexandre.torgue@st.com
References: <1391093744-19905-1-git-send-email-patrice.chotard@st.com> <1391093744-19905-2-git-send-email-patrice.chotard@st.com> <201401301935.16463.arnd@arndb.de>
In-Reply-To: <201401301935.16463.arnd@arndb.de>
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On Thursday 30 January 2014, Arnd Bergmann wrote:
> On Thursday 30 January 2014, Patrice CHOTARD wrote:
> > From: Alexandre TORGUE <alexandre.torgue@st.com>
> > 
> > This patch adds support to STiD127 SoC.
> > The main adaptation is the L2 cache way size compare to STiH41x SoCs.
> > 
> > Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
> > Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> > ---
> >  arch/arm/mach-sti/board-dt.c |    6 ++++++
> >  1 file changed, 6 insertions(+)
> 
> Wouldn't it be better to read this value from the l2 cache
> controller node? I'd assume there might be more SoCs that
> will need a similar change, so it's better to come up with
> a solution that doesn't involve changing the kernel every
> time.

Actually reading the code in this file shows that the L2 cache
initialization is the only nonstandard thing in there. We should
really find a way to get rid of the entire function.

Sorry if I missed the initial review, but can you explain
why this is needed to start with?

	Arnd
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