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From: Mikael Pettersson <mikpe@csd.uu.se>
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Date: Wed, 6 Nov 2002 11:53:59 +0100
To: george anzinger <george@mvista.com>
Cc: Ingo Molnar <mingo@elte.hu>,
       "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: NMI watchdog question.
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george anzinger writes:
 > In attempting to understand how the NMI watchdog works I
 > think I have found that:
 > 
 > a. the NMI interrupts are generated by the performance
 > counter in the cpu and
...
 > If this is so (and help me to understand if it is not), then
 > what do the timer interrupts going thru the IO_APIC have to
 > do with the NMI watchdog.

Before 2.4, the NMI watchdog was only available for SMP boxes,
since it used the I/O APIC to send NMIs to the CPUs. Then the
ability to use the *local* APIC on UP machines was introduced,
and with it the ability to drive the NMI watchdog from the CPU
itself, via performance counter overflow interrupts.

The NMI watchdog still supports both these modes of operation.
Typically, the performance counter + local APIC mode kicks in
when (a) you asked for it, or (b) you asked for the I/O APIC
mode but it wasn't available.

/Mikael
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