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Date: Wed, 06 Nov 2002 09:59:41 -0800
From: george anzinger <george@mvista.com>
Organization: Monta Vista Software
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To: Mikael Pettersson <mikpe@csd.uu.se>
CC: Ingo Molnar <mingo@elte.hu>,
       "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: NMI watchdog question.
References: <3DC8AD8A.20494DC0@mvista.com> <15816.62663.166644.782004@kim.it.uu.se>
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Mikael Pettersson wrote:
> 
> george anzinger writes:
>  > In attempting to understand how the NMI watchdog works I
>  > think I have found that:
>  >
>  > a. the NMI interrupts are generated by the performance
>  > counter in the cpu and
> ...
>  > If this is so (and help me to understand if it is not), then
>  > what do the timer interrupts going thru the IO_APIC have to
>  > do with the NMI watchdog.
> 
> Before 2.4, the NMI watchdog was only available for SMP boxes,
> since it used the I/O APIC to send NMIs to the CPUs. Then the
> ability to use the *local* APIC on UP machines was introduced,
> and with it the ability to drive the NMI watchdog from the CPU
> itself, via performance counter overflow interrupts.
> 
> The NMI watchdog still supports both these modes of operation.
> Typically, the performance counter + local APIC mode kicks in
> when (a) you asked for it, or (b) you asked for the I/O APIC
> mode but it wasn't available.

So then the NMI checks for timer interrupts being serviced
in this case?  But, still, why the turn off if the timer
does not go thru the APIC?  The case this came up in is an
SMP machine, but the test in apic.c shows that the PIT
interrupt does not go thru the APIC.  Leaving NMI on seems
to work, so I am wondering if this is just old code.
> 
> /Mikael
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-- 
George Anzinger   george@mvista.com
High-res-timers: 
http://sourceforge.net/projects/high-res-timers/
Preemption patch:
http://www.kernel.org/pub/linux/kernel/people/rml
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