Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933872AbaDIP1t (ORCPT ); Wed, 9 Apr 2014 11:27:49 -0400 Received: from gw-1.arm.linux.org.uk ([78.32.30.217]:55604 "EHLO pandora.arm.linux.org.uk" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S933372AbaDIP1s (ORCPT ); Wed, 9 Apr 2014 11:27:48 -0400 Date: Wed, 9 Apr 2014 16:27:11 +0100 From: Russell King - ARM Linux To: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= Cc: Jonas Jensen , "linux-arm-kernel@lists.infradead.org" , "arm@kernel.org" , "linux-kernel@vger.kernel.org" , ulli.kroll@googlemail.com, Arnd Bergmann , Olof Johansson Subject: Re: [PATCH] ARM: reinsert ARCH_MULTI_V4 Kconfig option Message-ID: <20140409152711.GT16119@n2100.arm.linux.org.uk> References: <1386922149-4561-1-git-send-email-jonas.jensen@gmail.com> <20131213095655.GB4360@n2100.arm.linux.org.uk> <20131213113903.GE4360@n2100.arm.linux.org.uk> <20140409150640.GQ16119@n2100.arm.linux.org.uk> <20140409151326.GY29751@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20140409151326.GY29751@pengutronix.de> User-Agent: Mutt/1.5.19 (2009-01-05) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 09, 2014 at 05:13:26PM +0200, Uwe Kleine-K?nig wrote: > Hello Russell, > > On Wed, Apr 09, 2014 at 04:06:40PM +0100, Russell King - ARM Linux wrote: > > On Wed, Apr 09, 2014 at 04:54:16PM +0200, Jonas Jensen wrote: > > > On 13 December 2013 12:39, Russell King - ARM Linux > > > wrote: > > > > I see what's causing this: the kuser helpers are using "bx lr" to return > > > > which will be undefined on non-Thumb CPUs. We generally cope fine with > > > > non-Thumb CPUs, conditionalising where necessary on HWCAP_THUMB or the > > > > T bit in the PSR being set. > > > > > > > > However, it looks like the kuser helpers got missed. As a check, please > > > > look at arch/arm/kernel/entry-armv.S, find the line with: > > > > > > > > .macro usr_ret, reg > > > > > > > > and ensure that the mov pc, \reg case always gets used. Please report > > > > back. > > > > > > Uwe and Arnd came up with a solution except it doesn't work when I test it. > > > > > > The suggested patch is: > > > > > > diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S > > > index 1879e8d..de15bfd 100644 > > > --- a/arch/arm/kernel/entry-armv.S > > > +++ b/arch/arm/kernel/entry-armv.S > > > @@ -739,6 +739,18 @@ ENDPROC(__switch_to) > > > > > > .macro usr_ret, reg > > > #ifdef CONFIG_ARM_THUMB > > > + /* > > > + * Having CONFIG_ARM_THUMB isn't a guarantee that the cpu has support > > > + * for Thumb and so the bx instruction. Use a mov if the address to > > > + * jump to is 32 bit aligned. (Note that this code is compiled in ARM > > > + * mode, so this is the right test.) > > > + */ > > > +#if defined(CONFIG_CPU_32v4) > > > + tst \reg, #3 > > > + moveq pc, \reg > > > + b . > > > +#endif > > > + > > > bx \reg > > > > What's wrong with: > > tst \reg, #3 > > moveq pc, \reg > > bx \reg > > > > rather than ending in an infinite loop? > The added b . was a test to check if the machine then hangs instead of > crashing. (And yes, that was the case, so it was tried to return to a > non-aligned address.) If it's called from ARM code, then \reg will contain a 4-byte aligned address. If it's called from Thumb code, \reg will contain a 2-byte aligned address with bit 0 *always* set. So, with the code originally quoted above, if the helper is called from thumb code, and CONFIG_CPU_32v4 is enabled, then we end up falling past the moveq to the "b ." and entering an infinite loop. -- FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly improving, and getting towards what was expected from it. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/