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Date: Mon, 14 Apr 2014 11:43:00 +0100
From: Will Deacon <will.deacon@arm.com>
To: Jianguo Wu <wujianguo@huawei.com>
Cc: "linux@arm.linux.org.uk" <linux@arm.linux.org.uk>,
        Wang Nan <wangnan0@huawei.com>,
        "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
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        Li Zefan <lizefan@huawei.com>,
        Catalin Marinas <Catalin.Marinas@arm.com>,
        Ben Dooks <ben.dooks@codethink.co.uk>,
        "linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
        marc.zyngier@arm.com
Subject: Re: [PATCH v2] ARM: mm: support big-endian page tables
Message-ID: <20140414104300.GA3530@arm.com>
References: <5301B4AF.1040305@huawei.com>
 <5327F75F.1010406@huawei.com>
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(catching up on old email)

On Tue, Mar 18, 2014 at 07:35:59AM +0000, Jianguo Wu wrote:
> Cloud you please take a look at this?

[...]

> On 2014/2/17 15:05, Jianguo Wu wrote:
> > When enable LPAE and big-endian in a hisilicon board, while specify
> > mem=384M mem=512M@7680M, will get bad page state:
> > 
> > Freeing unused kernel memory: 180K (c0466000 - c0493000)
> > BUG: Bad page state in process init  pfn:fa442
> > page:c7749840 count:0 mapcount:-1 mapping:  (null) index:0x0
> > page flags: 0x40000400(reserved)
> > Modules linked in:
> > CPU: 0 PID: 1 Comm: init Not tainted 3.10.27+ #66
> > [<c000f5f0>] (unwind_backtrace+0x0/0x11c) from [<c000cbc4>] (show_stack+0x10/0x14)
> > [<c000cbc4>] (show_stack+0x10/0x14) from [<c009e448>] (bad_page+0xd4/0x104)
> > [<c009e448>] (bad_page+0xd4/0x104) from [<c009e520>] (free_pages_prepare+0xa8/0x14c)
> > [<c009e520>] (free_pages_prepare+0xa8/0x14c) from [<c009f8ec>] (free_hot_cold_page+0x18/0xf0)
> > [<c009f8ec>] (free_hot_cold_page+0x18/0xf0) from [<c00b5444>] (handle_pte_fault+0xcf4/0xdc8)
> > [<c00b5444>] (handle_pte_fault+0xcf4/0xdc8) from [<c00b6458>] (handle_mm_fault+0xf4/0x120)
> > [<c00b6458>] (handle_mm_fault+0xf4/0x120) from [<c0013754>] (do_page_fault+0xfc/0x354)
> > [<c0013754>] (do_page_fault+0xfc/0x354) from [<c0008400>] (do_DataAbort+0x2c/0x90)
> > [<c0008400>] (do_DataAbort+0x2c/0x90) from [<c0008fb4>] (__dabt_usr+0x34/0x40)

[...]

> > The bug is happened in cpu_v7_set_pte_ext(ptep, pte):
> > when pte is 64-bit, for little-endian, will store low 32-bit in r2,
> > high 32-bit in r3; for big-endian, will store low 32-bit in r3,
> > high 32-bit in r2, this will cause wrong pfn stored in pte,
> > so we should exchange r2 and r3 for big-endian.

I believe that Marc (added to CC) has been running LPAE-enabled, big-endian
KVM guests without any issues, so it seems unlikely that we're storing the
PTEs backwards. Can you check the configuration of SCTLR.EE?

Will
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