Message-ID: <53504892.60404@hp.com>
Date: Thu, 17 Apr 2014 17:33:06 -0400
From: Waiman Long <waiman.long@hp.com>
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To: Peter Zijlstra <peterz@infradead.org>
CC: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>,
        "H. Peter Anvin" <hpa@zytor.com>, linux-arch@vger.kernel.org,
        x86@kernel.org, linux-kernel@vger.kernel.org,
        virtualization@lists.linux-foundation.org,
        xen-devel@lists.xenproject.org, kvm@vger.kernel.org,
        Paolo Bonzini <paolo.bonzini@gmail.com>,
        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
        "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>,
        Rik van Riel <riel@redhat.com>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Raghavendra K T <raghavendra.kt@linux.vnet.ibm.com>,
        David Vrabel <david.vrabel@citrix.com>,
        Oleg Nesterov <oleg@redhat.com>, Gleb Natapov <gleb@redhat.com>,
        Scott J Norton <scott.norton@hp.com>, Chegu Vinod <chegu_vinod@hp.com>
Subject: Re: [PATCH v9 05/19] qspinlock: Optimize for smaller NR_CPUS
References: <1397747051-15401-1-git-send-email-Waiman.Long@hp.com> <1397747051-15401-6-git-send-email-Waiman.Long@hp.com> <20140417155115.GQ11096@twins.programming.kicks-ass.net>
In-Reply-To: <20140417155115.GQ11096@twins.programming.kicks-ass.net>
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On 04/17/2014 11:51 AM, Peter Zijlstra wrote:
> On Thu, Apr 17, 2014 at 11:03:57AM -0400, Waiman Long wrote:
>> @@ -48,6 +53,9 @@
>>    * We can further change the first spinner to spin on a bit in the lock word
>>    * instead of its node; whereby avoiding the need to carry a node from lock to
>>    * unlock, and preserving API.
>> + *
>> + * N.B. The current implementation only supports architectures that allow
>> + *      atomic operations on smaller 8-bit and 16-bit data types.
>>    */
> Only for the _Q_PENDING_BITS == 8 case, the other case should still be
> fine.

Yes, but _Q_PENDING_BITS is controlled by NR_CPUS which, for almost all 
the distributions, is less than 16K which means _Q_PENDING_BITS will 
always be set to 8, especially for non-x86 architectures.

-Longman
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