Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754909AbaDUVsw (ORCPT ); Mon, 21 Apr 2014 17:48:52 -0400 Received: from mail-wg0-f49.google.com ([74.125.82.49]:45677 "EHLO mail-wg0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754822AbaDUVsi (ORCPT ); Mon, 21 Apr 2014 17:48:38 -0400 From: srinivas.kandagatla@linaro.org To: linux-mmc@vger.kernel.org Cc: Russell King , Chris Ball , Ulf Hansson , linux-kernel@vger.kernel.org, agross@quicinc.com, linux-arm-msm@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH RFC 07/12] mmc: mmci: Qcomm: Add 3 clock cycle delay after each register write Date: Mon, 21 Apr 2014 22:48:29 +0100 Message-Id: <1398116909-31517-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1398116624-31052-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1398116624-31052-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Srinivas Kandagatla This patch adds a 3 clock cycle delay required after writing to controller registers on Qualcomm SOCs. Without this delay cards are either not detected or fails as soon as card is put into data transfer mode. Signed-off-by: Srinivas Kandagatla --- drivers/mmc/host/mmci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 86bf330..2dc7581 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -168,6 +168,7 @@ static struct variant_data variant_qcom = { .fifosize = 16 * 4, .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, + .reg_write_delay = 3, .blksz_datactrl4 = true, .datalength_bits = 24, .blksz_datactrl4 = true, -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/