Date: Wed, 11 Jun 2014 13:54:13 +0200
From: Peter Zijlstra <peterz@infradead.org>
To: HATAYAMA Daisuke <d.hatayama@jp.fujitsu.com>
Cc: acme@kernel.org, mingo@redhat.com, paulus@samba.org, hpa@zytor.com,
        tglx@linutronix.de, x86@kernel.org, linux-kernel@vger.kernel.org,
        matt@console-pimps.org
Subject: Re: [PATCH] perf/x86/intel: ignore CondChgd bit to avoid false NMI
 handling
Message-ID: <20140611115413.GE3588@twins.programming.kicks-ass.net>
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 <20140611085448.GI3213@twins.programming.kicks-ass.net>
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On Wed, Jun 11, 2014 at 10:54:48AM +0200, Peter Zijlstra wrote:
> > I'm not sure about exact behavior of CondChgd bit, in particular when
> > this bit is set. Although I read Intel System Programmer's Manual to
> > figure out but I have yet completed that. At least, I think ignoring
> > CondChgd bit should be enough for NMI watchdog perspective.
>=20
> So yes, the SDM lists the bit as existing but never once mentions it
> outside of that, and its been doing that at least back to 2008.
>=20
> Ooh, I found it:
>=20
>   "The IA32_PERF_GLOBAL_STATUS MSR also provides a =E2=80=98sticky bit=E2=
=80=99 to
> indicate changes to the state of performance monitoring hardware (see
> Figure 18-29)."
>=20
> Which is of course completely useless, not to mention inconsistent with
> the later CondChgd name.
>=20
> HPA, can you explain wtf that bit does and why hatayama-san's ivb feels
> like having that set on boot?=20

Matt found in the MSR listing for GLOBAL_STATUS:

63 CondChg: status bits of this register has changed.  If CPUID.0AH: EAX[7:=
0] > 0

Which brings us to a grand total of 3 different names for this bit.

If it indeed does what it says on the tin, set every time the status
changes its like the most useless bit ever and I wonder why people
bothered to spend silicon on it.

In any case, the proposed patch seems fine, just needs a better
changelog.


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