Date: Thu, 12 Jun 2014 10:44:23 +0100
From: Russell King - ARM Linux <linux@arm.linux.org.uk>
To: Jisheng Zhang <jszhang@marvell.com>
Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
        ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
        sebastian.hesselbarth@gmail.com, alexandre.belloni@free-electrons.com,
        antoine.tenart@free-electrons.com, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency
	as 2 cycles
Message-ID: <20140612094423.GC23430@n2100.arm.linux.org.uk>
References: <1402565920-5636-1-git-send-email-jszhang@marvell.com>
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On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> For all BG2Q SoCs, 2 cycles is the best/correct value

It would be a good idea to set all these parameters if you need to set
them at all - in other words, setting arm,dirty-latency as well, as
that's all part of the timing specification.

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