Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755394AbaFPKog (ORCPT ); Mon, 16 Jun 2014 06:44:36 -0400 Received: from mail-wi0-f170.google.com ([209.85.212.170]:43400 "EHLO mail-wi0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755104AbaFPKoe (ORCPT ); Mon, 16 Jun 2014 06:44:34 -0400 Message-ID: <539ECA8C.4010007@gmail.com> Date: Mon, 16 Jun 2014 12:44:28 +0200 From: Sebastian Hesselbarth User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 To: =?UTF-8?B?QW50b2luZSBUw6luYXJ0?= , tj@kernel.org, kishon@ti.com CC: alexandre.belloni@free-electrons.com, thomas.petazzoni@free-electrons.com, zmxu@marvell.com, jszhang@marvell.com, linux-arm-kernel@lists.infradead.org, linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 6/7] ARM: berlin: add the AHCI node for the BG2Q References: <1402914392-6028-1-git-send-email-antoine.tenart@free-electrons.com> <1402914392-6028-7-git-send-email-antoine.tenart@free-electrons.com> In-Reply-To: <1402914392-6028-7-git-send-email-antoine.tenart@free-electrons.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/16/2014 12:26 PM, Antoine Ténart wrote: > The BG2Q has an AHCI SATA controller. Add the corresponding nodes > (AHCI, PHY) into its device tree. > > Signed-off-by: Antoine Ténart > --- > arch/arm/boot/dts/berlin2q.dtsi | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi > index 635a16a64cb4..3fb0d3935aec 100644 > --- a/arch/arm/boot/dts/berlin2q.dtsi > +++ b/arch/arm/boot/dts/berlin2q.dtsi > @@ -303,6 +303,34 @@ > clock-names = "refclk"; > }; > > + ahci: sata@e90000 { > + compatible = "generic-ahci"; > + reg = <0xe90000 0x1000>; > + interrupts = ; > + clocks = <&chip CLKID_SATA>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + sata0: sata-port@0 { > + reg = <0>; > + phys = <&sata_phy 0>; > + status = "disabled"; > + }; > + > + sata1: sata-port@1 { > + reg = <1>; > + phys = <&sata_phy 1>; > + status = "disabled"; > + }; > + }; > + > + sata_phy: phy@e900a0 { > + compatible = "marvell,berlin-sata-phy"; > + reg = <0xe900a0 0x200>; Antoine, I guess you'll also need clocks = <&chip CLKID_SATA>; here and corresponding code in the PHY driver. If SATA PHY is accessing SATA registers, disabling the clock will most likely lock-up the SoC. Sebastian > + #phy-cells = <1>; > + status = "disabled"; > + }; > + > apb@fc0000 { > compatible = "simple-bus"; > #address-cells = <1>; > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/