Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754903AbaGHNZK (ORCPT ); Tue, 8 Jul 2014 09:25:10 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:43552 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752753AbaGHNZG (ORCPT ); Tue, 8 Jul 2014 09:25:06 -0400 Message-ID: <53BBF0FA.1070006@ti.com> Date: Tue, 8 Jul 2014 09:24:10 -0400 From: Murali Karicheri User-Agent: Mozilla/5.0 (X11; Linux i686; rv:12.0) Gecko/20120430 Thunderbird/12.0.1 MIME-Version: 1.0 To: Murali Karicheri CC: , , , Santosh Shilimkar , Russell King , Grant Likely , Rob Herring , Mohit Kumar , Jingoo Han , Bjorn Helgaas , Pratyush Anand , Richard Zhu , Kishon Vijay Abraham I , Marek Vasut , Arnd Bergmann , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Randy Dunlap Subject: Re: [PATCH v3 4/5] PCI: designware: enhance dw core driver to support Keystone PCI host controller References: <1404164720-11066-1-git-send-email-m-karicheri2@ti.com> <1404164720-11066-5-git-send-email-m-karicheri2@ti.com> In-Reply-To: <1404164720-11066-5-git-send-email-m-karicheri2@ti.com> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/30/2014 05:45 PM, Murali Karicheri wrote: > Add API dw_pcie_v3_65_host_init() to support host controller initialization > for Keystone PCI driver. The Keystone PCI uses v3.65 version of the DW hardware > identified by compatibility string "dw,snps-pcie-v3.65". This allow for > different treatment for this version of the h/w during host initialization. > Key differences in v3.65 DW h/w are > 1. No ATU support > 2. Legacy and MSI irq functions are implemented in application > register space > 3. MSI interrupts are multiplexed over 8 IRQ lines to the Host side. > So a msi irq chip is needed and the irq domain ops ptr is passed in > dw_pcie_v3_65_host_init() to allow re-use of common MSI code in dw core. The > Keystone PCI host controller requires a modified pci scan function to allow > setup BAR0 for EP's access to MSI_IRQ register in application register to > raise MSI irq. So a ptr to pci hw ops struct is passed to the host init code. > > Keystone PCI controller re-uses the DW Core driver code wherever there is > common functionality. So this patch makes these functions global and added > their prototypes in pcie-designware.h to allow re-use on Keystone. > > Signed-off-by: Murali Karicheri > > CC: Santosh Shilimkar > CC: Russell King > CC: Grant Likely > CC: Rob Herring > CC: Mohit Kumar > CC: Jingoo Han > CC: Bjorn Helgaas > CC: Pratyush Anand > CC: Richard Zhu > CC: Kishon Vijay Abraham I > CC: Marek Vasut > CC: Arnd Bergmann > CC: Pawel Moll > CC: Mark Rutland > CC: Ian Campbell > CC: Kumar Gala > CC: Randy Dunlap > CC: Grant Likely > --- > .../devicetree/bindings/pci/designware-pcie.txt | 2 + > drivers/pci/host/pcie-designware.c | 39 ++++++++++++++++++-- > drivers/pci/host/pcie-designware.h | 7 ++++ > 3 files changed, 44 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt > index d0d15ee..0cb10c0 100644 > --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt > @@ -2,6 +2,8 @@ > > Required properties: > - compatible: should contain "snps,dw-pcie" to identify the core. > + Additionally contains "dw,snps-pcie-v3.65" to identify v3.65 version of the DW > + hardware. > - #address-cells: set to<3> > - #size-cells: set to<2> > - device_type: set to "pci" > diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c > index c11e4de..4dcbebe 100644 > --- a/drivers/pci/host/pcie-designware.c > +++ b/drivers/pci/host/pcie-designware.c > @@ -556,6 +556,37 @@ static int dw_pcie_msi_host_init(struct pcie_port *pp, > return 0; > } > > +int __init dw_pcie_v3_65_host_init(struct pcie_port *pp, struct hw_pci *hw, > + struct device_node *msi_irqc_np, > + const struct irq_domain_ops *msi_irq_ops) > +{ > + int ret = -EINVAL; > + > + /* check if compatible with v3.65 DW h/w */ > + if (!of_device_is_compatible(pp->dev->of_node, "dw,snps-pcie-v3.65")) { > + dev_err(pp->dev, > + "PCI Controller not compatible with v3.65 DW h/w\n"); > + goto out; > + } > + pp->version = DW_HW_V3_65; > + > + /* v3.65 PCI controller is expected to provide its own PCI h/w ops */ > + if (!hw || !msi_irq_ops) { > + dev_err(pp->dev, > + "v3.65 PCI Controllers doesn't provide %s\n", > + (hw == NULL) ? "PCI hw ops" : "PCI MSI irq domain ops"); > + goto out; > + } > + > + ret = dw_pcie_msi_host_init(pp, msi_irqc_np, msi_irq_ops); > + if (ret) > + goto out; > + > + ret = dw_pcie_common_host_init(pp, hw); > +out: > + return ret; > +} > + > int __init dw_pcie_host_init(struct pcie_port *pp) > { > int ret; > @@ -763,7 +794,7 @@ static struct pci_ops dw_pcie_ops = { > .write = dw_pcie_wr_conf, > }; > > -static int dw_pcie_setup(int nr, struct pci_sys_data *sys) > +int dw_pcie_setup(int nr, struct pci_sys_data *sys) > { > struct pcie_port *pp; > > @@ -786,7 +817,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys) > return 1; > } > > -static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) > +struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) > { > struct pci_bus *bus; > struct pcie_port *pp = sys_to_pcie(sys); > @@ -803,7 +834,7 @@ static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) > return bus; > } > > -static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) > +int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) > { > struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); > int irq; > @@ -815,7 +846,7 @@ static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) > return irq; > } > > -static void dw_pcie_add_bus(struct pci_bus *bus) > +void dw_pcie_add_bus(struct pci_bus *bus) > { > if (IS_ENABLED(CONFIG_PCI_MSI)) { > struct pcie_port *pp = sys_to_pcie(bus->sysdata); > diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h > index db0260f..2681826 100644 > --- a/drivers/pci/host/pcie-designware.h > +++ b/drivers/pci/host/pcie-designware.h > @@ -81,4 +81,11 @@ void dw_pcie_msi_init(struct pcie_port *pp); > int dw_pcie_link_up(struct pcie_port *pp); > void dw_pcie_setup_rc(struct pcie_port *pp); > int dw_pcie_host_init(struct pcie_port *pp); > +int dw_pcie_v3_65_host_init(struct pcie_port *pp, struct hw_pci *hw, > + struct device_node *msi_irqc_np, > + const struct irq_domain_ops *msi_irq_ops); > +int dw_pcie_setup(int nr, struct pci_sys_data *sys); > +struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys); > +void dw_pcie_add_bus(struct pci_bus *bus); > +int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); > #endif /* _PCIE_DESIGNWARE_H */ DT Maintainers, Could you provide your comments or Ack for the DT update made in this patch? Thanks Murali -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/