Date: Tue, 8 Jul 2014 10:56:39 -0400
From: Jason Cooper <jason@lakedaemon.net>
To: Jon Loeliger <loeliger@gmail.com>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        Thomas Gleixner <tglx@linutronix.de>, Rob Herring <robh+dt@kernel.org>,
        Grant Likely <grant.likely@linaro.org>
Subject: Re: Questions About a Semi-Soft irqchip Device
Message-ID: <20140708145639.GD13433@titan.lakedaemon.net>
References: <CAJgR-Bi2HX+aYVabaFLyu9QAnAS4RmQ7DvBtDHOawkfi08zycA@mail.gmail.com>
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Jon,

On Tue, Jul 08, 2014 at 09:02:14AM -0500, Jon Loeliger wrote:
> My IP block provides software-assignable interrupts.  That
> is, I have a large pool of interrupt sources, and a large pool
> of interrupt bits in the controller, but they are not physically
> tied together. Instead they are assigned by some driver as it
> initializes and allocates resources.  This, I think, means that
> I can not describe the interrupt  bindings in the DTS file.

Please take a look at the crossbar driver.  It's had quite a bit of
cleanup this cycle, so you may way to look at

  git://git.infradead.org/users/jcooper/linux.git irqchip/crossbar

It sounds very similar.

thx,

Jason.
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