Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752213AbaGJLZ5 (ORCPT ); Thu, 10 Jul 2014 07:25:57 -0400 Received: from mail-la0-f48.google.com ([209.85.215.48]:63965 "EHLO mail-la0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750989AbaGJLZz (ORCPT ); Thu, 10 Jul 2014 07:25:55 -0400 MIME-Version: 1.0 In-Reply-To: References: <1404982207-4707-1-git-send-email-harinik@xilinx.com> <1404982207-4707-2-git-send-email-harinik@xilinx.com> Date: Thu, 10 Jul 2014 13:25:53 +0200 X-Google-Sender-Auth: uaZe5URpPRs4CbOD920gNUGErNs Message-ID: Subject: Re: [RFC PATCH 1/2] spi: Add support for Zynq QSPI controller From: Geert Uytterhoeven To: Harini Katakam Cc: Mark Brown , Grant Likely , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , linux-spi , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-doc@vger.kernel.org" , David Woodhouse , Brian Norris , =?UTF-8?B?TWFyZWsgVmHFoXV0?= , Artem Bityutskiy , Geert Uytterhoeven , Sascha Hauer , Jingoo Han , Sourav Poddar , "michals@xilinx.com" , Punnaiah Choudary Kalluri Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Harini, On Thu, Jul 10, 2014 at 12:33 PM, Harini Katakam wrote: > On Thu, Jul 10, 2014 at 3:12 PM, Geert Uytterhoeven > wrote: >> On Thu, Jul 10, 2014 at 11:31 AM, Harini Katakam >> wrote: >>>>> + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | >>>>> + SPI_TX_DUAL | SPI_TX_QUAD; >>>> >>>> Your driver advertises Dual/Quad SPI Transfer capabilities, but it doesn't >>>> check spi_transfer.[tr]x_nbits? How can it determine when to enable Dual/Quad? >>> >>> Here the driver is just giving information that the controller support it. >>> The MTD layer enables dual/quad based on what the flash supports; quad >>> being the first priority >>> I understand that the spi core reads rx, tx-bus-width property and >>> master support flags and >>> performs the necessary checks. >> >> That's correct: as long as the rx, tx-bus-width properties do not indicate a >> Dual or Quad wiring, it won't be used. >> >> However, based on schematics, someone may set the rx, tx-bus-width properties >> to 4, which is correct, as DT describes the hardware. But this will fail to >> work. >> So I think it's safer not to announce Dual/Quad support in the driver until >> the actual driver support is there. > > OK. Correct me if I'm wrong but announcing this support in master->flags is > just to say the controller supports it - Like Punnaiah mentioned in the other > mail, nothing specific needs to be done from the controller driver to enable > dual/quad support. This is at the SOC/IP level. > I agree it might or might not be supported at board-level. IC. So this is not a generic SPI controller, but a controller meant for QSPI FLASHes? I.e. if you would connect a different device, the controller may unexpectedly use Dual or Quad mode if it sees a byte fly by that looks like a Quad SPI FLASH read command? > But that's based on the user's hardware. Should master->flags > really take this into consideration? You mean master->mode_bits? > BTW, I dint see master->mode_bits being used anywhere at the moment. It is used to match SPI controller and slave features, cfr. spi_setup() in drivers/spi/spi.c. If Dual/Quad is supported, the bits should be set. Else spi_setup() will clear the bits in the SPI slave's mode field, disabling Dual/Quad transfers. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/