Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754032AbaGKQnk (ORCPT ); Fri, 11 Jul 2014 12:43:40 -0400 Received: from mail-vc0-f179.google.com ([209.85.220.179]:37156 "EHLO mail-vc0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751043AbaGKQni (ORCPT ); Fri, 11 Jul 2014 12:43:38 -0400 MIME-Version: 1.0 In-Reply-To: <1405088313-20048-6-git-send-email-mperttunen@nvidia.com> References: <1405088313-20048-1-git-send-email-mperttunen@nvidia.com> <1405088313-20048-6-git-send-email-mperttunen@nvidia.com> Date: Fri, 11 Jul 2014 09:43:37 -0700 X-Google-Sender-Auth: dxodq96c44Ye968P0v_LdeIOXmQ Message-ID: Subject: Re: [PATCH 5/8] of: Add Tegra124 EMC bindings From: Andrew Bresticker To: Mikko Perttunen Cc: Peter De Schrijver , Prashant Gaikwad , Mike Turquette , Stephen Warren , Thierry Reding , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-tegra@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 11, 2014 at 7:18 AM, Mikko Perttunen wrote: > Add binding documentation for the nvidia,tegra124-emc device tree > node. > diff --git a/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt b/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt > +Required properties : > +- compatible : "nvidia,tegra124-emc". > +- reg : Should contain 1 or 2 entries: > + - EMC register set > + - MC register set : Required only if no node with > + 'compatible = "nvidia,tegra124-mc"' exists. The MC register set > + is first read from the MC node. If it doesn't exist, it is read > + from this property. > +- timings : Should contain 1 entry for each supported clock rate. > + Entries should be named "timing@n" where n is a 0-based increasing > + number. The timings must be listed in rate-ascending order. There are upcoming boards which support multiple DRAM configurations and require a separate set of timings for each configuration. Could we instead have multiple sets of timings with the proper one selected at runtime by RAM code, as reported by PMC_STRAPPING_OPT_A_0? Something like: emc { emc-table@0 { nvidia,ram-code = <0>; timing@0 { ... }; ... }; emc-table@1 { nvidia,ram-code = <4>; timing@0 { ... }; ... }; ... }; -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/