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Date: Mon, 14 Jul 2014 11:24:35 +0200
From: Thierry Reding <thierry.reding@gmail.com>
To: Mark Brown <broonie@kernel.org>
Cc: Tuomas Tynkkynen <ttynkkynen@nvidia.com>,
        Andrew Bresticker <abrestic@chromium.org>,
        "linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
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        Prashant Gaikwad <pgaikwad@nvidia.com>,
        Mike Turquette <mturquette@linaro.org>,
        Stephen Warren <swarren@wwwdotorg.org>,
        Viresh Kumar <viresh.kumar@linaro.org>,
        Peter De Schrijver <pdeschrijver@nvidia.com>,
        "Rafael J. Wysocki" <rjw@rjwysocki.net>
Subject: Re: [PATCH 01/13] clk: tegra: Add binding for the Tegra124 DFLL
 clocksource
Message-ID: <20140714092434.GA9755@ulmo>
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On Mon, Jul 14, 2014 at 10:12:33AM +0100, Mark Brown wrote:
> On Mon, Jul 14, 2014 at 10:38:56AM +0200, Thierry Reding wrote:
> > On Fri, Jul 11, 2014 at 08:21:27PM +0300, Tuomas Tynkkynen wrote:
>=20
> > > I don't think we can assume that each selector maps to a concrete reg=
ister
> > > value, though I'm not sure. include/linux/regulator/driver.h document=
s for
> > > @list_voltage "Selectors range from zero to one less
> > > regulator_desc.n_voltages." but maybe the consumer API could take dif=
ferent
> > > values.
>=20
> > I don't think the regulator API makes any guarantees that the selector
> > corresponds to a register value. Adding Mark Brown, maybe he can help
> > figure out the best way to do this.
>=20
> The selector value is opaque, it's entirely up to the driver to define
> it.  If you could tell me what "this" is I might be able to advise on
> how to do it.

Tegra124 (and later, also some earlier variants) have this DFLL clock
that can program a PMIC automatically depending on the CPU frequency.
This DT binding did propose putting this into device tree as a table of
<frequency value> pairs where the frequency corresponds to the CPU
frequency and the value is the register value to be programmed into the
PMIC by the DFLL hardware (there are two additional properties to define
the slave address and the register offset).

Andrew proposed that this table could instead be built by using
regulator_list_voltage() instead. However, due to the fact that the DFLL
hardware needs to know the immediate value to write into a register, the
requirement would be for a 1:1 mapping between selector and register
value. Given that the API needs to cover the general case I don't see
how it could practically ensure this.

Thierry

--+HP7ph2BbKc20aGI
Content-Type: application/pgp-signature

-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2

iQIcBAEBAgAGBQJTw6HSAAoJEN0jrNd/PrOhbFwP/03tePNKsD5IznjxmNgv6AMm
uot8qEnBu6iDp29m/HYArNbmtbsmpvVPiYdmV26DkpT21YP8qokTEmvKHwKSJ9gV
zeZlVKUXIRf04NfZLttOxWkQYIm3rx4WLlszJa4HE6i9K/bBKqrIgemffLW7aq54
vlDYd6QMOM6fIEJUk6+tZ5LyhwVhuiNFOJWVt+onhI0bxAMU+oiHCD//z82JXNQq
Je05gDP0KqGUtM7xjDrCH0c+pQ1OVcUK1veDAmuvSJvlR3Rlf6fLn4lKlKwSSEqj
nHAtUdoDvqIrFj5KISWpuYkrkk4K6Kg0PQ4Ux/ojWEqoecAzKCnhIgzW2IL3tIUA
16tq6tn6pc6CGSchljYNG0P2zxmweBROtzPL0rBSCmxT052mK1+G6RXNMGE8dpie
U+XuXYxlweGxMVJk1OIUAg/Y2o4EBz6LUjcpmOGuB3YqeJ9qV2bD9kKQadHtYSl7
dvt1ZFdaYA6iHrFZYJ/k1QvmNey4b5sri4vTJ7d9PDJBPL07xsljDx83nXMFoC+Y
XI2GVaA2/pbsce5CTSzBcaWMp6ipaMrb6WrOsYO3b52VBELOZhO5ix54W2kZykTC
3zFh6OGqZJAXfULF7nRi/Q6IC0dVuipIHCuZIRhfvEilE0sad1zszCTtFTM/HE+v
m8SKSlf9hUiGbK7D+iHH
=8il+
-----END PGP SIGNATURE-----

--+HP7ph2BbKc20aGI--
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