Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934797AbaGQQkl (ORCPT ); Thu, 17 Jul 2014 12:40:41 -0400 Received: from mailout4.w1.samsung.com ([210.118.77.14]:56771 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934662AbaGQQjz (ORCPT ); Thu, 17 Jul 2014 12:39:55 -0400 X-AuditID: cbfec7f5-b7f626d000004b39-83-53c7fc58e2c2 From: Tomasz Figa To: linux-samsung-soc@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kukjin Kim , Russell King - ARM Linux , lauraa@codeaurora.org, linux-omap@vger.kernel.org, linus.walleij@linaro.org, santosh.shilimkar@ti.com, tony@atomide.com, drake@endlessm.com, Marek Szyprowski , Tomasz Figa , loeliger@gmail.com, Tomasz Figa Subject: [PATCH v3 7/7] ARM: dts: exynos4: Add nodes for L2 cache controller Date: Thu, 17 Jul 2014 18:39:02 +0200 Message-id: <1405615142-21426-8-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.9.3 In-reply-to: <1405615142-21426-1-git-send-email-t.figa@samsung.com> References: <1405615142-21426-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrMLMWRmVeSWpSXmKPExsVy+t/xq7oRf44HG8w5ZG7xaP5jZoveBVfZ LLZ3zmC3mPJnOZPFpsfXWC0u75rDZjF7ST+LxYzz+5gsbl/mtTi3fQuLxdojd9ktXvetYbZY P+M1i8WqXX8YLfZf8XLg92hp7mHz+PZ1EovH5b5eJo9F37M8ds66y+5x59oeNo/NS+o9+ras YvQ4fmM7k8fnTXIBXFFcNimpOZllqUX6dglcGRd7OlkLDvJUTLvyjrGBcT5XFyMnh4SAiUT3 3NXMELaYxIV769lAbCGBpYwSj1ekdDFyAdl9TBKTP/eBJdgE1CQ+NzwCs0UEVCU+ty1gByli FjjALHFh0wMWkISwgI9ET/sTsKksQEWnnpxhBLF5BZwkPi15CbVNTqJ32xswm1PAWWLu/sdQ m50ktrQtYJrAyLuAkWEVo2hqaXJBcVJ6rpFecWJucWleul5yfu4mRkhAf93BuPSY1SFGAQ5G JR7eH1zHg4VYE8uKK3MPMUpwMCuJ8GbfBwrxpiRWVqUW5ccXleakFh9iZOLglGpgDKw49uUO +z7ezvv3P742Fak9H6hy7u3aWefDHj3ddGXKef5dV6wu7n52a6mTbcT5bzcE9q0yrUrqk/v1 e/L2K/5b//kXpqod2X9Z5Dhf3MpVS/612oksmcffoldXnDK3X5dnxhSRhJ9T6hIP7zyUqm7C qfi7qWzK7pgLk9z47/mkX7Uu9vd6JKrEUpyRaKjFXFScCAA/JnKIRgIAAA== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds device tree nodes for L2 cache controller present on Exynos4 SoCs. Signed-off-by: Tomasz Figa --- arch/arm/boot/dts/exynos4210.dtsi | 9 +++++++++ arch/arm/boot/dts/exynos4x12.dtsi | 14 ++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index ee3001f..99970ab 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -54,6 +54,15 @@ reg = <0x10023CA0 0x20>; }; + l2c: l2-cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <2 2 1>; + }; + gic: interrupt-controller@10490000 { cpu-offset = <0x8000>; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index c5a943d..ddffefe 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -60,6 +60,20 @@ reg = <0x10023CA0 0x20>; }; + l2c: l2-cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <3 2 1>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <1>; + arm,prefetch-drop = <1>; + arm,prefetch-offset = <7>; + }; + clock: clock-controller@10030000 { compatible = "samsung,exynos4412-clock"; reg = <0x10030000 0x20000>; -- 1.9.3 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/