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Date: Wed, 07 Feb 2001 21:06:47 -0800
From: "H. Peter Anvin" <hpa@transmeta.com>
Organization: Transmeta Corporation
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To: Mikael Pettersson <mikpe@csd.uu.se>
CC: macro@ds2.pg.gda.pl, linux-kernel@vger.kernel.org, mingo@redhat.com,
        vandrove@vc.cvut.cz
Subject: Re: [PATCH] Re: UP APIC reenabling vs. cpu type detection ordering
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Mikael Pettersson wrote:
> 
> H. Peter Anvin wrote:
> 
> >"Maciej W. Rozycki" wrote:
> >...
> >>  It might be viable just to delete the test altogether, though and just
> >> trap #GP(0) on the MSR access.  For the sake of simplicity.  If a problem
> >> with a system ever arizes, we may handle it then.
> >>
> >>  Note that we still have to choose appropriate vendor-specific PeMo
> >> handling and an event for the NMI watchdog anyway.
> >
> >Right... if that is the case then it seems reasonable.
> 
> No, poking into MSRs not explicitly defined on the current CPU is
> inherently unsafe. I have several x86 CPU data sheets here in front
> of me which say the same thing: "Don't write to undocumented MSRs."
> You cannot assume that every single x86 out there stays clear of
> all Intel-defined MSRs. Intel has also expanded this set over time:
> older designs may not even have known about the APIC_BASE MSR.
> 

You misread me.  "In that case it seems reasonable to do vendor-specific
detection."

	-hpa

-- 
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
"Unix gives you enough rope to shoot yourself in the foot."
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