Date: Thu, 31 Jul 2014 09:16:25 +0200
From: Ingo Molnar <mingo@kernel.org>
To: "Yan, Zheng" <zheng.z.yan@intel.com>
Cc: linux-kernel@vger.kernel.org, a.p.zijlstra@chello.nl, acme@infradead.org,
        eranian@google.com, andi@firstfloor.org, Jiri Olsa <jolsa@redhat.com>
Subject: Re: [PATCH v4 0/9] perf, x86: large PEBS interrupt threshold
Message-ID: <20140731071625.GA4209@gmail.com>
References: <1406789104-25863-1-git-send-email-zheng.z.yan@intel.com>
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* Yan, Zheng <zheng.z.yan@intel.com> wrote:

> This patch series implements large PEBS interrupt threshold. For some
> limited cases, it can significantly reduce the sample overhead. Please
> read patch 6's commit message for more information.
> 
> changes since v1:
>   - drop patch 'perf, core: Add all PMUs to pmu_idr'
>   - add comments for case that multiple counters overflow simultaneously
> changes since v2:
>   - rename perf_sched_cb_{enable,disable} to perf_sched_cb_user_{inc,dec} 
>   - use flag to indicate auto reload mechanism
>   - move codes that setup PEBS sample data to separate function
>   - output the PEBS records in batch 
>   - enable this for All (PEBS capable) hardware 
>   - more description for the multiplex
> changes since v3:
>   - ignore conflicting PEBS record

Please include performance measurements, 'significantly reduces sample 
overhead' is a totally inadequate description to judge this patch set.

Please also include total diffstat in the 0/N mail.

Thanks,

	Ingo
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