Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752694AbaJDPdo (ORCPT ); Sat, 4 Oct 2014 11:33:44 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:51466 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750973AbaJDPdn (ORCPT ); Sat, 4 Oct 2014 11:33:43 -0400 From: Leonid Yegoshin To: Peter Zijlstra CC: "linux-mips@linux-mips.org" , Zubair Kakakhel , "david.daney@cavium.com" , "paul.gortmaker@windriver.com" , "davidlohr@hp.com" , "macro@linux-mips.org" , "chenhc@lemote.com" , "zajec5@gmail.com" , James Hogan , "keescook@chromium.org" , "alex@alex-smith.me.uk" , "tglx@linutronix.de" , "blogic@openwrt.org" , "jchandra@broadcom.com" , Paul Burton , Qais Yousef , "linux-kernel@vger.kernel.org" , "ralf@linux-mips.org" , Markos Chandras , "manuel.lauss@gmail.com" , "akpm@linux-foundation.org" , "lars.persson@axis.com" Subject: Re: [PATCH 0/3] MIPS executable stack protection Thread-Topic: [PATCH 0/3] MIPS executable stack protection Thread-Index: Ac/f6JBasxw0os/VaEewjedDoGfZbg== Date: Sat, 4 Oct 2014 15:33:36 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Content-Type: text/plain; charset="utf-8" Content-ID: MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id s94FXnUP024427 Peter Zijlstra wrote: >> It sets up a per-thread 'VDSO' page and appropriate TLB support. > So traditionally we've always avoided per-thread pages like that. > What makes it worth it on MIPS? MIPS has branch delay slots - it is an instruction after branch which is executed before branch is taken. If branch fails due to FPU unavailability then that instruction should be emulated as well as branch itself. However, MIPS allows to have a customisable coprocessor 2 instructions and it is impractical to emulate it and big amount of other traditional MIPS instructions inside of kernel. So, some per thread space is needed to put instruction into it, enclose it with a return kernel call and switch temporary execution into it. Currently, this space is space at SP register (user stack) but it prevents switching stack as non-executable. Handle another stack set (one stack per thread) in common user map is impractical because of management, scalability and performance difficulties. ????{.n?+???????+%?????ݶ??w??{.n?+????{??G?????{ay?ʇڙ?,j??f???h?????????z_??(?階?ݢj"???m??????G????????????&???~???iO???z??v?^?m???? ????????I?