Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751904AbaJOXog (ORCPT ); Wed, 15 Oct 2014 19:44:36 -0400 Received: from mail-qa0-f52.google.com ([209.85.216.52]:34133 "EHLO mail-qa0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751293AbaJOXof (ORCPT ); Wed, 15 Oct 2014 19:44:35 -0400 MIME-Version: 1.0 Date: Wed, 15 Oct 2014 16:44:34 -0700 Message-ID: Subject: PCIe PASID (Process Address Space ID) and iommu code From: Kallol Biswas To: linux-kernel@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Resending, as message got bounced for html content. -------------------------------------------- Hi, PCIe has introduced PASID TLP Prefix. There are two ECNs on this. It seems that AMD iommu code makes use of PASID. Is there a device that utilizes this TLP prefix? PASID allocation and management within a device is not clear to me. How does device know which PASID to issue for which virtual address? Who makes the association? Must be software/OS, but how? There is no table for this like MSI-X table. Any pointer/documentation will be appreciated. Regards, -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/