From: "Li.Xiubo@freescale.com" <Li.Xiubo@freescale.com>
To: Shengchao Guo <Shawn.Guo@freescale.com>
CC: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>
Subject: RE: [PATCH v3] ARM: ls1021a: add gating clocks to IP blocks.
Thread-Topic: [PATCH v3] ARM: ls1021a: add gating clocks to IP blocks.
Thread-Index: AQHP1yw1xpt6riX400mCXn9hhSG2j5wRjisAgCCUt7A=
Date: Thu, 16 Oct 2014 02:30:31 +0000
Message-ID: <458d4826bf9a4d678480ae3d9660380e@BY2PR0301MB0613.namprd03.prod.outlook.com>
References: <1411476275-9164-1-git-send-email-Li.Xiubo@freescale.com>
 <20140925085403.GG6405@dragon>
In-Reply-To: <20140925085403.GG6405@dragon>
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Hi Shawn,

[...]
> > +						DCFG_CCSR_DEVDISR1,
> > +						ls1021a_clk_shift(0));
> 
> I think we can ignore the 80 columns warning and put these on one line
> to make the code a bit easier to read.
> 

Yes, it looks better, but in the FSL's internal Gerrit it will be a little
Harder to merge this patch in SDK, the Jenkins will check this and then return
failure.


Thanks,

BRs
Xiubo

> > +	clks[LS1021A_CLK_ESDHC_EN] = ls1021a_clk_gate("esdhc_en", "dummy",
> > +						DCFG_CCSR_DEVDISR1,
> > +						ls1021a_clk_shift(2));
[...]
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