Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932812AbaJXPFa (ORCPT ); Fri, 24 Oct 2014 11:05:30 -0400 Received: from mail-ob0-f174.google.com ([209.85.214.174]:59869 "EHLO mail-ob0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932576AbaJXPFO (ORCPT ); Fri, 24 Oct 2014 11:05:14 -0400 MIME-Version: 1.0 In-Reply-To: <20141024092832.GD20534@e104818-lin.cambridge.arm.com> References: <1413993983-17310-1-git-send-email-mathieu.poirier@linaro.org> <20141022164454.GI15370@e104818-lin.cambridge.arm.com> <20141024092832.GD20534@e104818-lin.cambridge.arm.com> Date: Fri, 24 Oct 2014 09:05:13 -0600 Message-ID: Subject: Re: [PATCH] ARM: supplementing IO accessors with 64 bit capability From: Mathieu Poirier To: Catalin Marinas Cc: "linux@arm.linux.org.uk" , "stefano.stabellini@eu.citrix.com" , "ezequiel.garcia@free-electrons.com" , Liviu Dudau , "thomas.petazzoni@free-electrons.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 24 October 2014 03:28, Catalin Marinas wrote: > On Wed, Oct 22, 2014 at 08:10:27PM +0100, Mathieu Poirier wrote: >> On 22 October 2014 18:44, Catalin Marinas wrote: >> > On Wed, Oct 22, 2014 at 05:06:23PM +0100, mathieu.poirier@linaro.org wrote: >> >> +static inline void __raw_writeq(u64 val, volatile void __iomem *addr) >> >> +{ >> >> + asm volatile("strd %1, %0" >> >> + : "+Qo" (*(volatile u64 __force *)addr) >> >> + : "r" (val)); >> >> +} >> >> + >> >> +static inline u64 __raw_readq(const volatile void __iomem *addr) >> >> +{ >> >> + u64 val; >> >> + asm volatile("ldrd %1, %0" >> >> + : "+Qo" (*(volatile u64 __force *)addr), >> >> + "=r" (val)); >> >> + return val; >> >> +} >> >> +#endif >> > >> > I'm curious why you need these. Do you have a device that needs a 64-bit >> > single access or you are trying to read two consecutive registers? >> >> The fundamental data size of Coresight STM32 for ARMv7 is >> implementation defined and can be 32 or 64bit. As such stimulus ports >> can support transaction sizes of up to 64 bit. > > The STM programmer's model spec recommends something else (though I find > the "3.6 Data sizes" chapter a bit confusing): > > To ensure that code is portable between processor micro-architectures > and system implementations, ARM recommends that only the native data > size of the machine is used, and smaller sizes. For the 32-bit ARMv7 > architecture, only 8, 16, and 32-bit transfers are recommended. For an > ARMv8 processor that supports the AArch64 Execution state, it is > recommended that the fundamental data size of 64-bits is implemented. > > Which means that you should not use readq/writeq on a 32-bit system. Not quite. ARM documentation IHI0054B (ARM System Trace Macrocell: Programmers' Model Architecture Specification) stipulate that "For systems with an ARMv7 processor, ARM recommends configuration 1 or configuration 2.", where configuration 2 has a fundamental size of 64 bit. Mathieu > > -- > Catalin -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/