Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934423AbaJ2QYg (ORCPT ); Wed, 29 Oct 2014 12:24:36 -0400 Received: from mail-wi0-f179.google.com ([209.85.212.179]:52422 "EHLO mail-wi0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933523AbaJ2QYc (ORCPT ); Wed, 29 Oct 2014 12:24:32 -0400 From: Tomeu Vizoso To: linux-tegra@vger.kernel.org Cc: Javier Martinez Canillas , Mikko Perttunen , Tomeu Vizoso , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Stephen Warren , Thierry Reding , Alexandre Courbot , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 06/13] of: Add Tegra124 EMC bindings Date: Wed, 29 Oct 2014 17:22:24 +0100 Message-Id: <1414599796-30597-7-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1414599796-30597-1-git-send-email-tomeu.vizoso@collabora.com> References: <1414599796-30597-1-git-send-email-tomeu.vizoso@collabora.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mikko Perttunen Add binding documentation for the nvidia,tegra124-emc device tree node. Signed-off-by: Mikko Perttunen Signed-off-by: Tomeu Vizoso --- v2: * Specify the unit addresses for the timings and timing nodes --- .../bindings/memory-controllers/tegra-emc.txt | 118 +++++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt b/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt new file mode 100644 index 0000000..fe64d57 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt @@ -0,0 +1,118 @@ +NVIDIA Tegra124 SoC EMC (external memory controller) +==================================================== + +Required properties : +- compatible : Should be "nvidia,tegra124-emc". +- reg : physical base address and length of the controller's registers. +- nvidia,memory-controller : phandle of the MC driver. + +The node should contain a "timings" subnode for each supported RAM type (see +field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address being its +RAM_CODE. + +Required properties for "timings" nodes : +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used +for. + +Each "timings" node should contain a "timing" subnode for every supported EMC +clock rate. The "timing" subnodes should have the clock rate in Hz as their unit +address. + +Required properties for "timing" nodes : +- clock-frequency : Should contain the memory clock rate in Hz. +- The following properties contain EMC timing characterization values (specified +in the board documentation) : + - nvidia,emc-zcal-cnt-long + - nvidia,emc-auto-cal-interval + - nvidia,emc-ctt-term-ctrl + - nvidia,emc-cfg + - nvidia,emc-cfg-2 + - nvidia,emc-sel-dpd-ctrl + - nvidia,emc-cfg-dig-dll + - nvidia,emc-bgbias-ctl0 + - nvidia,emc-auto-cal-config + - nvidia,emc-auto-cal-config2 + - nvidia,emc-auto-cal-config3 + - nvidia,emc-mode-reset + - nvidia,emc-mode-1 + - nvidia,emc-mode-2 + - nvidia,emc-mode-4 +- nvidia,emc-configuration : EMC timing characterization data to be written to +the EMC registers, as specified by the board documentation. + +Example SoC include file: + +/ { + emc@0,7001b000 { + compatible = "nvidia,tegra124-emc"; + reg = <0x0 0x7001b000 0x0 0x1000>; + + nvidia,memory-controller = <&mc>; + }; +}; + +Example board file: + +/ { + emc@0,7001b000 { + timings@3 { + nvidia,ram-code = <3>; + + timing@12750000 { + clock-frequency = <12750000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-cfg-dig-dll = <0x002c0068>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000003 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + >; + }; + + timing@20400000 { + clock-frequency = <20400000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-cfg-dig-dll = <0x002c0068>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-auto-cal-config = <0x00000000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0xa1430000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000005 + 0x00000000 + 0x00000000 + 0x00000000 + >; + }; + }; + }; +}; -- 1.9.3 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/