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Date: Wed, 29 Oct 2014 09:56:54 -0700
Message-ID: <CAL1qeaGm1Ma=B-gJV2ovnLNYFooq6bv12rODq4d8cGtKLeNy-g@mail.gmail.com>
Subject: Re: [PATCH V3 2/4] of: Add binding document for MIPS GIC
From: Andrew Bresticker <abrestic@chromium.org>
To: Qais Yousef <qais.yousef@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>, Rob Herring <robh+dt@kernel.org>,
        Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>,
        Ian Campbell <ijc+devicetree@hellion.org.uk>,
        Kumar Gala <galak@codeaurora.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        John Crispin <blogic@openwrt.org>, David Daney <ddaney.cavm@gmail.com>,
        Linux-MIPS <linux-mips@linux-mips.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
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Sender: linux-kernel-owner@vger.kernel.org

On Wed, Oct 29, 2014 at 4:01 AM, Qais Yousef <qais.yousef@imgtec.com> wrote:
> On 10/29/2014 12:12 AM, Andrew Bresticker wrote:
>>
>> +- mti,available-cpu-vectors : Specifies the list of CPU interrupt vectors
>> +  to which the GIC may route interrupts.  May contain up to 6 entries,
>> one
>> +  for each of the CPU's hardware interrupt vectors.  Valid values are 2 -
>> 7.
>> +  This property is ignored if the CPU is started in EIC mode.
>> +
>
>
> Wouldn't it be better to have this in the reversed sense ie:
> mti,nonavailable-cpu-vectors? I think the assumption that by default they're
> all available unless something else is connected to them which is unlikely
> in most cases. It can be made optional property then.
>
> I don't have a strong opinion about it though.

Actually, I think I like the reversed sense as well.  Perhaps
"mti,reserved-cpu-vectors"?
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