Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757509AbaJ2Vei (ORCPT ); Wed, 29 Oct 2014 17:34:38 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:29124 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756291AbaJ2Veg (ORCPT ); Wed, 29 Oct 2014 17:34:36 -0400 Date: Wed, 29 Oct 2014 21:34:31 +0000 From: James Hogan To: Andrew Bresticker CC: Ralf Baechle , Rob Herring , Pawel Moll , Mark Rutland , "Ian Campbell" , Kumar Gala , Thomas Gleixner , Jason Cooper , Daniel Lezcano , John Crispin , David Daney , Qais Yousef , Linux-MIPS , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Paul Subject: Re: [PATCH V3 2/4] of: Add binding document for MIPS GIC Message-ID: <20141029213431.GF30260@jhogan-linux.le.imgtec.org> References: <1414541562-10076-1-git-send-email-abrestic@chromium.org> <1414541562-10076-3-git-send-email-abrestic@chromium.org> <5450B1B1.5070301@imgtec.com> <5451201C.9090106@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.22 (2013-10-16) X-Originating-IP: [192.168.154.101] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Andrew, On Wed, Oct 29, 2014 at 10:25:27AM -0700, Andrew Bresticker wrote: > On Wed, Oct 29, 2014 at 10:13 AM, James Hogan wrote: > > On 29/10/14 16:55, Andrew Bresticker wrote: > >> On Wed, Oct 29, 2014 at 2:21 AM, James Hogan wrote: > >>> Please lets not do this unless it's actually necessary (which AFAICT it > >>> really isn't). > >> > >> The point of this was to future-proof these bindings and I though that > >> CPU type was the best way to indicate version in the compatible > >> string. This is also how it's done for the ARM GIC and arch timers. > >> Perhaps the best thing to do is to require both a core-specific > >> ("mti,interaptiv-gic") and generic ("mti,gic") compatible string and > >> just match on the generic one for now until there's a need to use the > >> core-specific one. Thoughts? > > > > FPGA boards like Malta are something else to consider (when it is > > eventually converted to DT - Paul on CC knows more than me). You might > > load an interAptiv, or a proAptiv, or a P5600 bitstream, and the gic > > setup will be pretty much the same I think, since e.g. the address > > depends on where it is convenient to put it in the address space of the > > platform. > > Ah, I didn't realize that the CPU bitstream could be changed > independently of the GIC. To clarify, the GIC is still closely bound to the CPU and contained within the FPGA bitstream. The register interface should I believe always comply with some version of the GIC architecture specification, and I don't think anybody wants per-bitstream DT files / kernels, so in practice the way the GIC is set up for Malta (how interrupt lines are connected up and where in address space GIC can go) is unlikely to become incompatible. Cheers James -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/