Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753255AbaKGUKU (ORCPT ); Fri, 7 Nov 2014 15:10:20 -0500 Received: from 18.mo4.mail-out.ovh.net ([188.165.54.143]:60338 "EHLO mo4.mail-out.ovh.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751285AbaKGUKS (ORCPT ); Fri, 7 Nov 2014 15:10:18 -0500 X-Greylist: delayed 14997 seconds by postgrey-1.27 at vger.kernel.org; Fri, 07 Nov 2014 15:10:17 EST From: Julien CHAUVEAU To: Heiko Stuebner , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC...), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC...), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND...), linux-kernel@vger.kernel.org (open list) Cc: Julien CHAUVEAU Subject: [PATCH] ARM: dts: rockchip: add pinctrl nodes for SPDIF, LCDC, CIF, HDMI, USB and GPS Date: Fri, 7 Nov 2014 16:19:49 +0100 Message-Id: <1415373589-11650-1-git-send-email-julien.chauveau@neo-technologies.fr> X-Mailer: git-send-email 2.1.0 X-Ovh-Tracer-Id: 16369740221320790241 X-Ovh-Remote: 193.248.240.88 (laubervilliers-656-01-116-88.w193-248.abo.wanadoo.fr) X-Ovh-Local: 213.186.33.20 (ns0.ovh.net) X-OVH-SPAMSTATE: OK X-OVH-SPAMSCORE: -100 X-OVH-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeejhedrheehucetufdoteggodetrfcurfhrohhfihhlvgemucfqggfjnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeejhedrheehucetufdoteggodetrfcurfhrohhfihhlvgemucfqggfjnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On RK3066, add pinctrl nodes for SPDIF, LCDC1, CIF0/1, HDMI and USB. On RK3188, add pinctrl nodes for SPDIF, LCDC1, CIF and GPS. At the same time, add some missing pinctrl for SDMMC0 and SDMMC1 and fix the unit addresses of GPIO0 and GPIO1 banks in rk3188.dtsi. Signed-off-by: Julien CHAUVEAU --- arch/arm/boot/dts/rk3066a.dtsi | 198 +++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3188.dtsi | 148 +++++++++++++++++++++++++++++- 2 files changed, 344 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 0e99470..899b5ef 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -430,6 +430,14 @@ , ; }; + + sd0_rst: sd0-rst { + rockchip,pins = ; + }; + + sd0_pwr: sd0-pwr { + rockchip,pins = ; + }; }; sd1 { @@ -459,6 +467,18 @@ , ; }; + + sd1_pwr: sd1-pwr { + rockchip,pins = ; + }; + + sd1_bckpwr: sd1-bckpwr { + rockchip,pins = ; + }; + + sd1_int: sd1-int { + rockchip,pins = ; + }; }; i2s0 { @@ -496,6 +516,184 @@ ; }; }; + + spdif { + spdif_tx: spdif-tx { + rockchip,pins = ; + }; + }; + + usb { + otg_drv_vbus: otg-drv-vbus { + rockchip,pins = ; + }; + + host_drv_vbus: host-drv-vbus { + rockchip,pins = ; + }; + }; + + /* No IOMUX for LCDC0 */ + + lcdc1 { + lcdc1_clk: lcdc1-clk { + rockchip,pins = , /* lcd1_dclk */ + , /* lcd1_den */ + , /* lcd1_hsync */ + ; /* lcd1_vsync */ + }; + + lcdc1_rgb565: lcdc1-rgb565 { + rockchip,pins = , /* D0 = B0 */ + , /* D1 = B1 */ + , /* D2 = B2 */ + , /* D3 = B3 */ + , /* D4 = B4 */ + , /* D5 = G0 */ + , /* D6 = G1 */ + , /* D7 = G2 */ + , /* D8 = G3 */ + , /* D9 = G4 */ + , /* D10 = G5 */ + , /* D11 = R0 */ + , /* D12 = R1 */ + , /* D13 = R2 */ + , /* D14 = R3 */ + ; /* D15 = R4 */ + }; + + lcdc1_rgb666: lcdc1-rgb666 { + rockchip,pins = , /* D0 = B0 */ + , /* D1 = B1 */ + , /* D2 = B2 */ + , /* D3 = B3 */ + , /* D4 = B4 */ + , /* D5 = B5 */ + , /* D6 = G0 */ + , /* D7 = G1 */ + , /* D8 = G2 */ + , /* D9 = G3 */ + , /* D10 = G4 */ + , /* D11 = G5 */ + , /* D12 = R0 */ + , /* D13 = R1 */ + , /* D14 = R2 */ + , /* D15 = R3 */ + , /* D16 = R4 */ + ; /* D17 = R5 */ + }; + + lcdc1_rgb888: lcdc1-rgb888 { + rockchip,pins = , /* D0 = B0 */ + , /* D1 = B1 */ + , /* D2 = B2 */ + , /* D3 = B3 */ + , /* D4 = B4 */ + , /* D5 = B5 */ + , /* D6 = B6 */ + , /* D7 = B7 */ + , /* D8 = G0 */ + , /* D9 = G1 */ + , /* D10 = G2 */ + , /* D11 = G3 */ + , /* D12 = G4 */ + , /* D13 = G5 */ + , /* D14 = G6 */ + , /* D15 = G7 */ + , /* D16 = R0 */ + , /* D17 = R1 */ + , /* D18 = R2 */ + , /* D19 = R3 */ + , /* D20 = R4 */ + , /* D21 = R5 */ + , /* D22 = R6 */ + ; /* D23 = R7 */ + }; + }; + + cif0 { + /* No IOMUX for CIF0 clock in, vsync and href */ + + cif0_clk_out: cif0-clk-out { + rockchip,pins = ; /* cif0_clkout */ + }; + + /* No IOMUX for CIF0 data pins 2-9 (width 8) */ + + cif0_bus10: cif0-bus-width10 { + rockchip,pins = , /* cif0_d0 */ + ; /* cif0_d1 */ + }; + + cif0_bus12: cif0-bus-width12 { + rockchip,pins = , /* cif0_d0 */ + , /* cif0_d1 */ + , /* cif0_d10 */ + ; /* cif0_d11 */ + }; + }; + + cif1 { + cif1_clk_in: cif1-clk-in { + rockchip,pins = , /* cif1_vsync */ + , /* cif1_href */ + ; /* cif1_clkin */ + }; + + cif1_clk_out: cif1-clk-out { + rockchip,pins = ; /* cif1_clkout */ + }; + + cif1_bus8: cif1-bus-width8 { + rockchip,pins = , /* cif1_d2 */ + , /* cif1_d3 */ + , /* cif1_d4 */ + , /* cif1_d5 */ + , /* cif1_d6 */ + , /* cif1_d7 */ + , /* cif1_d8 */ + ; /* cif1_d9 */ + }; + + cif1_bus10: cif1-bus-width10 { + rockchip,pins = , /* cif1_d0 */ + , /* cif1_d1 */ + , /* cif1_d2 */ + , /* cif1_d3 */ + , /* cif1_d4 */ + , /* cif1_d5 */ + , /* cif1_d6 */ + , /* cif1_d7 */ + , /* cif1_d8 */ + ; /* cif1_d9 */ + }; + + cif1_bus12: cif1-bus-width12 { + rockchip,pins = , /* cif1_d0 */ + , /* cif1_d1 */ + , /* cif1_d2 */ + , /* cif1_d3 */ + , /* cif1_d4 */ + , /* cif1_d5 */ + , /* cif1_d6 */ + , /* cif1_d7 */ + , /* cif1_d8 */ + , /* cif1_d9 */ + , /* cif1_d10 */ + ; /* cif1_d11 */ + }; + }; + + hdmi { + hdmi_hpd { + rockchip,pins = ; /* hot plug in */ + }; + + hdmi_i2c { + rockchip,pins = , /* DDC SCL */ + ; /* DDC SDA */ + }; + }; }; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index b24e04f..fb05d76 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -111,7 +111,7 @@ #size-cells = <1>; ranges; - gpio0: gpio0@0x2000a000 { + gpio0: gpio0@2000a000 { compatible = "rockchip,rk3188-gpio-bank0"; reg = <0x2000a000 0x100>; interrupts = ; @@ -124,7 +124,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@0x2003c000 { + gpio1: gpio1@2003c000 { compatible = "rockchip,gpio-bank"; reg = <0x2003c000 0x100>; interrupts = ; @@ -379,6 +379,10 @@ rockchip,pins = ; }; + sd0_rst: sd0-rst { + rockchip,pins = ; + }; + sd0_pwr: sd0-pwr { rockchip,pins = ; }; @@ -412,6 +416,18 @@ rockchip,pins = ; }; + sd1_pwr: sd1-pwr { + rockchip,pins = ; + }; + + sd1_bckpwr: sd1-bckpwr { + rockchip,pins = ; + }; + + sd1_int: sd1-int { + rockchip,pins = ; + }; + sd1_bus1: sd1-bus-width1 { rockchip,pins = ; }; @@ -434,6 +450,134 @@ ; }; }; + + spdif { + spdif_tx: spdif-tx { + rockchip,pins = ; + }; + }; + + /* No IOMUX for LCDC0 */ + + lcdc1 { + lcdc1_clk: lcdc1-clk { + rockchip,pins = , /* lcd1_dclk */ + , /* lcd1_den */ + , /* lcd1_hsync */ + ; /* lcd1_vsync */ + }; + + lcdc1_rgb565: lcdc1-rgb565 { + rockchip,pins = , /* D0 = B0 */ + , /* D1 = B1 */ + , /* D2 = B2 */ + , /* D3 = B3 */ + , /* D4 = B4 */ + , /* D5 = G0 */ + , /* D6 = G1 */ + , /* D7 = G2 */ + , /* D8 = G3 */ + , /* D9 = G4 */ + , /* D10 = G5 */ + , /* D11 = R0 */ + , /* D12 = R1 */ + , /* D13 = R2 */ + , /* D14 = R3 */ + ; /* D15 = R4 */ + }; + + lcdc1_rgb666: lcdc1-rgb666 { + rockchip,pins = , /* D0 = B0 */ + , /* D1 = B1 */ + , /* D2 = B2 */ + , /* D3 = B3 */ + , /* D4 = B4 */ + , /* D5 = B5 */ + , /* D6 = G0 */ + , /* D7 = G1 */ + , /* D8 = G2 */ + , /* D9 = G3 */ + , /* D10 = G4 */ + , /* D11 = G5 */ + , /* D12 = R0 */ + , /* D13 = R1 */ + , /* D14 = R2 */ + , /* D15 = R3 */ + , /* D16 = R4 */ + ; /* D17 = R5 */ + }; + + lcdc1_rgb888: lcdc1-rgb888 { + rockchip,pins = , /* D0 = B0 */ + , /* D1 = B1 */ + , /* D2 = B2 */ + , /* D3 = B3 */ + , /* D4 = B4 */ + , /* D5 = B5 */ + , /* D6 = B6 */ + , /* D7 = B7 */ + , /* D8 = G0 */ + , /* D9 = G1 */ + , /* D10 = G2 */ + , /* D11 = G3 */ + , /* D12 = G4 */ + , /* D13 = G5 */ + , /* D14 = G6 */ + , /* D15 = G7 */ + , /* D16 = R0 */ + , /* D17 = R1 */ + , /* D18 = R2 */ + , /* D19 = R3 */ + , /* D20 = R4 */ + , /* D21 = R5 */ + , /* D22 = R6 */ + ; /* D23 = R7 */ + }; + }; + + cif { + /* CIF clock in, vsync and href are not accessible through pinctrl */ + + cif_clk_out: cif-clk-out { + rockchip,pins = ; + }; + + /* CIF data pins 2-9 (width 8) are not accessible through pinctrl */ + + cif_bus10: cif-bus-width10 { + rockchip,pins = , /* cif_d0 */ + ; /* cif_d1 */ + }; + + cif_bus12: cif-bus-width12 { + rockchip,pins = , /* cif_d0 */ + , /* cif_d1 */ + , /* cif_d10 */ + ; /* cif_d11 */ + }; + + cif_bus16: cif-bus-width16 { + rockchip,pins = , /* cif_d0 */ + , /* cif_d1 */ + , /* cif_d10 */ + ; /* cif_d11 */ + /* No IOMUX for CIF data pins 12-15 */ + }; + }; + + gps { + gps_mag: gps-mag { + rockchip,pins = ; + }; + + gps_sig: gps-sig { + rockchip,pins = ; + }; + + gps_rfclk: gps-rfclk { + rockchip,pins = ; + }; + }; }; }; -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/