Message-ID: <546A5F6A.7070704@sr71.net>
Date: Mon, 17 Nov 2014 12:49:46 -0800
From: Dave Hansen <dave@sr71.net>
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To: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
CC: linux-kernel@vger.kernel.org, dave.hansen@linux.intel.com, x86@kernel.org,
        a.p.zijlstra@chello.nl, paulus@samba.org, acme@kernel.org,
        jkenisto@us.ibm.com, srikar@linux.vnet.ibm.com, tglx@linutronix.de,
        ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net
Subject: Re: [PATCH] x86: remove arbitrary instruction size limit in instruction
 decoder
References: <20141112225352.D49917A8@viggo.jf.intel.com> <5464C4FD.60705@hitachi.com>
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On 11/13/2014 06:49 AM, Masami Hiramatsu wrote:
> (2014/11/13 7:53), Dave Hansen wrote:
>> The kprobes code probably needs to be looked at here a bit more
>> carefully.  This patch still respects the MAX_INSN_SIZE limit
>> there but the kprobes code does look like it might be able to
>> be a bit more strict than it currently is.
> 
> Would you mean kprobes can copy shorter? Maybe, but I think current
> one is enough because it is on a cold path.
> OK, at least this looks good to me.

As it stands now, if you happened to be decoding an instruction which is
short and it was *JUST* before a memory hole, I think it could oops the
kernel.

This doesn't look like it is very common (or maybe even possible) in
practice.

>> Note: the v10 version of the MPX patches I just posted depends
>> on this patch.
> 
> BTW, current insn decoder doesn't support MPX... That should be
> updated (add bnd* to x86-insn-map.txt)

I think they're in there already:

> grep -i bnd arch/x86/lib/x86-opcode-map.txt
1a: BNDCL Ev,Gv | BNDCU Ev,Gv | BNDMOV Gv,Ev | BNDLDX Gv,Ev,Gv
1b: BNDCN Ev,Gv | BNDMOV Ev,Gv | BNDMK Gv,Ev | BNDSTX Ev,GV,Gv

Or were there others you were thinking of?
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