Message-ID: <546FA0C4.1000402@intel.com>
Date: Fri, 21 Nov 2014 12:29:56 -0800
From: Dave Hansen <dave.hansen@intel.com>
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To: Vikas Shivappa <vikas.shivappa@linux.intel.com>,
        linux-kernel@vger.kernel.org
CC: vikas.shivappa@intel.com, hpa@zytor.com, tglx@linutronix.de,
        mingo@kernel.org, tj@kernel.org, matt.flemming@intel.com,
        will.auld@intel.com, peterz@infradead.org
Subject: Re: [PATCH] x86: Intel Cache Allocation Technology support
References: <1416445539-24856-1-git-send-email-vikas.shivappa@linux.intel.com>
In-Reply-To: <1416445539-24856-1-git-send-email-vikas.shivappa@linux.intel.com>
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Sender: linux-kernel-owner@vger.kernel.org

On 11/19/2014 05:05 PM, Vikas Shivappa wrote:
> +	/*
> +	 * Hard code the checks and values for HSW SKUs.
> +	 * Unfortunately! have to check against only these brand name strings.
> +	 */
> +
> +	for (i = 0; i < 5; i++)
> +		if (!strcmp(hsw_brandstrs[i], c->x86_model_id)) {
> +			c->x86_cqe_closs = 4;
> +			c->x86_cqe_cbmlength = 20;
> +			return true;
> +		}

Please use ARRAY_SIZE() here.  Otherwise, I guarantee the next string
you add to hsw_brandstrs[] gets silently ignored.

Are there really only 5 CPUs?  This:

> http://ark.intel.com/products/family/78583/Intel-Xeon-Processor-E5-v3-Family#@Server

lists 32 skus.
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