From: Jingchang Lu <jingchang.lu@freescale.com>
To: Vinod Koul <vinod.koul@intel.com>
CC: "dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCHv4] dmaengine: fsl-edma: fixup reg offset and hw S/G
 support in big-endian model
Thread-Topic: [PATCHv4] dmaengine: fsl-edma: fixup reg offset and hw S/G
 support in big-endian model
Thread-Index: AQHP7dxw0ZXsnje90ESiN3180LVrWZyHROAAgAAEwWA=
Date: Tue, 9 Dec 2014 09:35:47 +0000
Message-ID: <BN3PR0301MB1236551BC121795218B2EAB387650@BN3PR0301MB1236.namprd03.prod.outlook.com>
References: <1413968035-12855-1-git-send-email-jingchang.lu@freescale.com>
 <20141209091248.GA16827@intel.com>
In-Reply-To: <20141209091248.GA16827@intel.com>
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Hi, Vinod,
  
  Many thanks!
  I resend the patch just before I saw this email, please ignore the
resend one since they are the same.


Thanks and Best Regards,
Jingchang

>-----Original Message-----
>From: Vinod Koul [mailto:vinod.koul@intel.com]
>Sent: Tuesday, December 09, 2014 5:13 PM
>To: Lu Jingchang-B35083
>Cc: dmaengine@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>linux-kernel@vger.kernel.org
>Subject: Re: [PATCHv4] dmaengine: fsl-edma: fixup reg offset and hw S/G
>support in big-endian model
>
>On Wed, Oct 22, 2014 at 04:53:55PM +0800, Jingchang Lu wrote:
>> The offset of all 8-/16-bit registers in big-endian eDMA model are
>> swapped in a 32-bit size opposite those in the little-endian model.
>>
>> The hardware Scatter/Gather requires the subsequent TCDs stored in
>> memory in little endian independent of the register endian model, the
>> eDMA engine will do the swap if need.
>>
>> This patch also use regular assignment for tcd variables r/w instead
>> of with io function previously that may not always be true.
>Applied, thanks
>
>--
>~Vinod


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