From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
To: <tglx@linutronix.de>, <mingo@redhat.com>, <hpa@zytor.com>,
        <tony.luck@intel.com>, <bp@alien8.de>, <dougthompson@xmission.com>,
        <mchehab@osg.samsung.com>, <x86@kernel.org>,
        <linux-kernel@vger.kernel.org>, <linux-edac@vger.kernel.org>
CC: <dave.hansen@linux.intel.com>, <mgorman@suse.de>, <bp@suse.de>,
        <riel@redhat.com>, <jacob.w.shin@gmail.com>,
        Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Subject: [PATCH 3/3] edac, mce_amd_inj: Inject errors only on NBC for bank 4 errors
Date: Mon, 22 Dec 2014 14:10:12 -0600
Message-ID: <1419279012-4754-4-git-send-email-Aravind.Gopalakrishnan@amd.com>
In-Reply-To: <1419279012-4754-1-git-send-email-Aravind.Gopalakrishnan@amd.com>
References: <1419279012-4754-1-git-send-email-Aravind.Gopalakrishnan@amd.com>
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For Fam10h onwards, bank4 MCE are reported only to the node base
cores. This patch modifies the do_inject code path to take care
of this.

Refer D18F3x44[NbMcaToMstCpuEn] on BKDGs of Fam10h and later for
clarifications on the reporting of MC4 errors only to NBC MSRs.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
---
 drivers/edac/mce_amd_inj.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/edac/mce_amd_inj.c b/drivers/edac/mce_amd_inj.c
index 0bd91a8..d4aa14f 100644
--- a/drivers/edac/mce_amd_inj.c
+++ b/drivers/edac/mce_amd_inj.c
@@ -126,6 +126,7 @@ static void do_inject(void)
 {
 	u64 mcg_status = 0;
 	unsigned int cpu = i_mce.extcpu;
+	int saved_cpu = -1;
 	u8 b = i_mce.bank;
 
 	if (!(i_mce.inject_flags & MCJ_EXCEPTION)) {
@@ -143,22 +144,34 @@ static void do_inject(void)
 	if (!(i_mce.status & MCI_STATUS_PCC))
 		mcg_status |= MCG_STATUS_RIPV;
 
-	toggle_hw_mce_inject(cpu, true);
-
 	wrmsr_on_cpu(cpu, MSR_IA32_MCG_STATUS,
 		     (u32)mcg_status, (u32)(mcg_status >> 32));
 
+	/*
+	 * for Fam10h+, if bank = 4, then we should write to NBC MSR
+	 * for multi-node processors else to core 0 for single node processors
+	 */
+	if (boot_cpu_data.x86 >= 0x10 && b == 4) {
+		saved_cpu = cpu;
+		cpu = amd_get_nbc_for_cpu(cpu);
+	}
+
+	toggle_hw_mce_inject(cpu, true);
+
 	wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b),
 		     (u32)i_mce.status, (u32)(i_mce.status >> 32));
 
 	wrmsr_on_cpu(cpu, MSR_IA32_MCx_ADDR(b),
 		     (u32)i_mce.addr, (u32)(i_mce.addr >> 32));
 
+	toggle_hw_mce_inject(cpu, false);
+
+	if (saved_cpu != -1)
+		cpu = saved_cpu;
+
 	wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b),
 		     (u32)i_mce.misc, (u32)(i_mce.misc >> 32));
 
-	toggle_hw_mce_inject(cpu, false);
-
 	smp_call_function_single(cpu, trigger_mce, NULL, 0);
 
 err:
-- 
2.0.2

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