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Date: Fri, 03 Jan 2003 13:47:29 -0800
From: "Martin J. Bligh" <mbligh@aracnet.com>
To: Ron cooper <rcooper@jamesconeyisland.com>
cc: linux-kernel@vger.kernel.org
Subject: Re: Gigabit/SMP performance problem
Message-ID: <26860000.1041630449@flay>
In-Reply-To: <200301031549.29549.rcooper@jamesconeyisland.com>
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>> Dual what Xeon? I presume a P4 thing. Can you cat /proc/interrupts?
>> Are you using the irq_balance code? If so, I think you'll only use
>> 1 cpu to process all the interrupts from each gigabit card. Not that
>> you have much choice, since Intel broke the P4's interrupt routing.
> 
> You got my attention with this statement.  I've have Dual Xeon Prestonias on 
> an I860 chipset (IWill dp400).  cat  /proc/interrupts indeed shows CPU0 as 
> processing all IRQ's instead of sharing them with CPU1 on a 2.4.x kernel.
> 
> Is there a work around for this, or is this *really* a problem?  Some say it 
> might be a problem depending on how many interrupts need to be processed per 
> second.  Others imply that cpu0 catching  the irq's might be a good thing.

Right - depends what you're doing. You can look at irq balance (in 2.5 
or 2.4-ac), but I don't like it as a solution much. Or you could try 
programming the TPR (were some patches floating around). Would be interesting
to get some perf measurments against people using the TPR patches (is more
expensive to set on a P4). Or someone from Intel posted some code recently
that seemed to do more intelligent things, but I haven't had the time to
look closely. If you want to experiment with that, I'm sure people would
be interested in the results.
 
> I happen to have PIII's using VIA chipsets that dont have this issue with 
> proc/interrupts.  This is very annonying, but I wonder if it is worth 
> worrying about.

P3's aren't as brain damaged.

M.

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