Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754932AbbBDKKg (ORCPT ); Wed, 4 Feb 2015 05:10:36 -0500 Received: from down.free-electrons.com ([37.187.137.238]:56333 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753001AbbBDKKd (ORCPT ); Wed, 4 Feb 2015 05:10:33 -0500 Date: Wed, 4 Feb 2015 11:10:28 +0100 From: Boris Brezillon To: Maxime Ripard Cc: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Ezequiel Garcia , Brian Norris , linux-mtd@lists.infradead.org, Boris Brezillon , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Tawfik Bayouk , Nadav Haklai , Lior Amsalem , linux-kernel@vger.kernel.org, Sudhakar Gundubogula , Seif Mazareeb , Subject: Re: [PATCH v2 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining Message-ID: <20150204111028.2f0bd376@bbrezillon> In-Reply-To: <1422284164-16867-2-git-send-email-maxime.ripard@free-electrons.com> References: <1422284164-16867-1-git-send-email-maxime.ripard@free-electrons.com> <1422284164-16867-2-git-send-email-maxime.ripard@free-electrons.com> X-Mailer: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2623 Lines: 77 Hi Maxime, On Mon, 26 Jan 2015 15:56:03 +0100 Maxime Ripard wrote: > The NDDB register holds the data that are needed by the read and write > commands. > > However, during a read PIO access, the datasheet specifies that after each 32 > bits read in that register, when BCH is enabled, we have to make sure that the > RDDREQ bit is set in the NDSR register. > > This fixes an issue that was seen on the Armada 385, and presumably other mvebu > SoCs, when a read on a newly erased page would end up in the driver reporting a > timeout from the NAND. > > Cc: # v3.14 > Signed-off-by: Maxime Ripard > --- > drivers/mtd/nand/pxa3xx_nand.c | 45 ++++++++++++++++++++++++++++++++++++------ > 1 file changed, 39 insertions(+), 6 deletions(-) > > diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c > index 96b0b1d27df1..e6918befb951 100644 > --- a/drivers/mtd/nand/pxa3xx_nand.c > +++ b/drivers/mtd/nand/pxa3xx_nand.c > @@ -23,6 +23,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -480,6 +481,38 @@ static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) > nand_writel(info, NDCR, ndcr | int_mask); > } > > +static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) > +{ > + u32 *dst = (u32 *)data; > + > + if (info->ecc_bch) { > + while (len--) { > + u32 timeout; > + > + *dst++ = nand_readl(info, NDDB); > + > + /* > + * According to the datasheet, when reading > + * from NDDB with BCH enabled, after each 32 > + * bits reads, we have to make sure that the > + * NDSR.RDDREQ bit is set > + */ I know the datasheet says this bit should be checked after each transfer, but I wonder if we shouldn't check it before reading the data. What happens if you drain all the data available in the FIFO ? Is the controller still setting the RDDREQ bit ? Moreover, the datasheet says this RDDREQ bit should be checked after each 32 bytes (not 32 bits) transfer. Testing it after each readl call shouldn't hurt though. Best Regards, Boris -- Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/