Date: Wed, 4 Feb 2015 18:13:57 -0800
From: Vinod Koul <vinod.koul@intel.com>
To: Andrew Bresticker <abrestic@chromium.org>
Cc: Dan Williams <dan.j.williams@intel.com>, Rob Herring <robh+dt@kernel.org>,
        Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>,
        Ian Campbell <ijc+devicetree@hellion.org.uk>,
        Kumar Gala <galak@codeaurora.org>,
        Grant Likely <grant.likely@linaro.org>,
        James Hartley <james.hartley@imgtec.com>,
        James Hogan <james.hogan@imgtec.com>,
        Ezequiel Garcia <ezequiel.garcia@imgtec.com>,
        Damien Horsley <Damien.Horsley@imgtec.com>,
        Arnd Bergmann <arnd@arndb.de>, dmaengine@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V3 0/2] dmaengine: Support for IMG MDC
Message-ID: <20150205021357.GN4489@intel.com>
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On Thu, Dec 11, 2014 at 02:59:15PM -0800, Andrew Bresticker wrote:
> This series adds support for the IMG Multi-threaded DMA Controller (MDC)
> which is found on IMG SoCs.  Currently this driver only supports the
> variant found on the MIPS-based Pistachio SoC.
> 
> The MDC supports slave and memory-to-memory transfers on up to 32 channels.
> Requests from channels are handled by MDC threads.  Thread assignments are
> per-channel and are specified in the device-tree.
> 
> Tested on a platform based on the Pistachio SoC with additional patches.
> Support for Pistachio will be submitted later.  Slave DMA was tested
> with the recently submitted IMG SPFI driver [1] and memory-to-memory
> DMA was tested with the dmatest module.
> 
Applied, thanks

-- 
~Vinod

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