Message-id: <54D32A1A.8020202@samsung.com>
Date: Thu, 05 Feb 2015 14:00:18 +0530
From: Pankaj Dubey <pankaj.dubey@samsung.com>
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To: Chanwoo Choi <cw00.choi@samsung.com>, s.nawrocki@samsung.com,
        tomasz.figa@gmail.com, mturquette@linaro.org
Cc: kgene@kernel.org, inki.dae@samsung.com, chanho61.park@samsung.com,
        sw0312.kim@samsung.com, linux-samsung-soc@vger.kernel.org,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [v3,3/9] clk: samsung: exynos5433: Add clocks for CMU_MSCL domain
References: <1422922437-7414-4-git-send-email-cw00.choi@samsung.com>
In-reply-to: <1422922437-7414-4-git-send-email-cw00.choi@samsung.com>
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Hi Chanwoo,

On Tuesday 03 February 2015 05:43 AM, Chanwoo Choi wrote:
> This patch adds the mux/divider/gate clocks for CMU_MSCL domain which
> generates the clocks for M2M (Memory to Memory) scaler, JPEG IPs.
>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Acked-by: Inki Dae <inki.dae@samsung.com>
>
> ---
> .../devicetree/bindings/clock/exynos5433-clock.txt |  20 +++
>   drivers/clk/samsung/clk-exynos5433.c               | 185 +++++++++++++++++++++
>   include/dt-bindings/clock/exynos5433.h             |  41 ++++-
>   3 files changed, 245 insertions(+), 1 deletion(-)
>

Verified clock tree, clock register and bitfield settings against UM.
Changes looks OK to me.

Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>

Thanks,
Pankaj Dubey
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