Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755656AbbBFOTh (ORCPT ); Fri, 6 Feb 2015 09:19:37 -0500 Received: from down.free-electrons.com ([37.187.137.238]:41624 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755599AbbBFOTf (ORCPT ); Fri, 6 Feb 2015 09:19:35 -0500 Message-ID: <54D4CCEB.5090009@free-electrons.com> Date: Fri, 06 Feb 2015 11:17:15 -0300 From: Ezequiel Garcia User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-Version: 1.0 To: Boris Brezillon , Brian Norris CC: Maxime Ripard , Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , linux-mtd@lists.infradead.org, Boris Brezillon , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Tawfik Bayouk , Nadav Haklai , Lior Amsalem , linux-kernel@vger.kernel.org, Sudhakar Gundubogula , Seif Mazareeb , stable@vger.kernel.org, Rob Herring Subject: Re: [PATCH v2 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining References: <1422284164-16867-1-git-send-email-maxime.ripard@free-electrons.com> <1422284164-16867-2-git-send-email-maxime.ripard@free-electrons.com> <20150204111028.2f0bd376@bbrezillon> <20150206010835.GB30781@ld-irv-0074> <20150206091307.1162b123@bbrezillon> In-Reply-To: <20150206091307.1162b123@bbrezillon> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4529 Lines: 114 On 02/06/2015 05:13 AM, Boris Brezillon wrote: > Hi Brian, > > On Thu, 5 Feb 2015 17:08:35 -0800 > Brian Norris wrote: > >> + Rob >> >> This patch has conflicts with an ARM64-preparation from Rob. I'd like to >> get this patch in first, as it's a bugfix. But I'd like to settle >> Boris's comments first. >> >> (Regarding the request to get this into 3.19: not likely. Judging by the >> age of the "bug", it's not massively critical, and we have no time. It >> can get out through -stable once it's gotten proper review and testing.) >> >> On Wed, Feb 04, 2015 at 11:10:28AM +0100, Boris Brezillon wrote: >>> On Mon, 26 Jan 2015 15:56:03 +0100 >>> Maxime Ripard wrote: >>> >>>> The NDDB register holds the data that are needed by the read and write >>>> commands. >>>> >>>> However, during a read PIO access, the datasheet specifies that after each 32 >>>> bits read in that register, when BCH is enabled, we have to make sure that the >>>> RDDREQ bit is set in the NDSR register. >>>> >>>> This fixes an issue that was seen on the Armada 385, and presumably other mvebu >>>> SoCs, when a read on a newly erased page would end up in the driver reporting a >>>> timeout from the NAND. >>>> >>>> Cc: # v3.14 >>>> Signed-off-by: Maxime Ripard >>>> --- >>>> drivers/mtd/nand/pxa3xx_nand.c | 45 ++++++++++++++++++++++++++++++++++++------ >>>> 1 file changed, 39 insertions(+), 6 deletions(-) >>>> >>>> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c >>>> index 96b0b1d27df1..e6918befb951 100644 >>>> --- a/drivers/mtd/nand/pxa3xx_nand.c >>>> +++ b/drivers/mtd/nand/pxa3xx_nand.c >>>> @@ -23,6 +23,7 @@ >>>> #include >>>> #include >>>> #include >>>> +#include >>>> #include >>>> #include >>>> #include >>>> @@ -480,6 +481,38 @@ static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) >>>> nand_writel(info, NDCR, ndcr | int_mask); >>>> } >>>> >>>> +static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) >>>> +{ >>>> + u32 *dst = (u32 *)data; >>>> + >>>> + if (info->ecc_bch) { >>>> + while (len--) { >>>> + u32 timeout; >>>> + >>>> + *dst++ = nand_readl(info, NDDB); >>>> + >>>> + /* >>>> + * According to the datasheet, when reading >>>> + * from NDDB with BCH enabled, after each 32 >>>> + * bits reads, we have to make sure that the >>>> + * NDSR.RDDREQ bit is set >>>> + */ >>> >>> I know the datasheet says this bit should be checked after each >>> transfer, but I wonder if we shouldn't check it before reading the data. >>> What happens if you drain all the data available in the FIFO ? Is the >>> controller still setting the RDDREQ bit ? >>> >>> Moreover, the datasheet says this RDDREQ bit should be checked after >>> each 32 bytes (not 32 bits) transfer. >>> Testing it after each readl call shouldn't hurt though. >> >> Seems like that could quite possibly kill performance unnecessarily, >> couldn't it? But then, PIO is probably not that fast in the first >> place... > > Absolutety, my point was, it shouldn't hurt from a functional POV, but > yes it will definitely impact performances. > But that's not the first thing I would rework of if you're concerned > about performances: when doing PIO read/write, the page read/write > operations (I mean the part reading the internal fifo) are all done in > interrupt context (called from pxa3xx_nand_irq), and doing this will > prevent any other interrupt from taking place while you are > draining/filling the FIFO :-(. But NAND operations are serialized, and there won't be any other interrupt for the controller until it's has drained the FIFO. So this doesn't really seem to hit performance to me. Or am I missing anything here? > An alternative would be to move this part into the read/write_buf > functions, but that's a lot of work... > Yeah, indeed. This also has other benefits. As we discussed on IRC, it would allow to support raw writes (i.e. ECC off). -- Ezequiel Garc?a, Free Electrons Embedded Linux, Kernel and Android Engineering http://free-electrons.com -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/