Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757574AbbBFPQM (ORCPT ); Fri, 6 Feb 2015 10:16:12 -0500 Received: from metis.ext.pengutronix.de ([92.198.50.35]:40149 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754741AbbBFPQK (ORCPT ); Fri, 6 Feb 2015 10:16:10 -0500 Date: Fri, 6 Feb 2015 16:15:42 +0100 From: Sascha Hauer To: Matthias Brugger Cc: Henry Chen , Rob Herring , Mike Turquette , srv_heupstream , Sascha Hauer , James Liao , huang eddie , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Catalin Marinas , Vladimir Murzin , Ashwin Chaugule , "Joe.C" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , linux-mediatek@lists.infradead.org Subject: Re: [PATCH v4 0/7] clk: Add common clock support for Mediatek MT8135 and MT8173. Message-ID: <20150206151542.GO12209@pengutronix.de> References: <1422594798-13375-1-git-send-email-henryc.chen@mediatek.com> <20150206103033.GS18908@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Sent-From: Pengutronix Hildesheim X-URL: http://www.pengutronix.de/ X-IRC: #ptxdist @freenode X-Accept-Language: de,en X-Accept-Content-Type: text/plain X-Uptime: 16:14:15 up 114 days, 2:27, 159 users, load average: 0.01, 0.05, 0.05 User-Agent: Mutt/1.5.21 (2010-09-15) X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c0 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1245 Lines: 27 On Fri, Feb 06, 2015 at 03:20:35PM +0100, Matthias Brugger wrote: > > I don't really understand the "as part of the clk driver part". I now > > have replaced the devm_regmap_init_mmio with syscon_node_to_regmap > > in the pericfg / infracfg drivers. Is that all that you want or do you > > want me to move the source code to drivers/clk/mediatek? > > Yes, I propose to move the source code to drivers/clk/mediatek. > Please have a look on other clock drivers which implement the reset > controller, e.g. rockchip. Ok, I'm halfway through implementing this, but let's have weekend first. Henry, If you're fine with this I'll change your clock series according to Matthias suggestions. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/