Date: Tue, 10 Feb 2015 08:47:18 -0600
From: Felipe Balbi <balbi@ti.com>
To: Yunzhi Li <lyz@rock-chips.com>
CC: <johnyoun@synopsys.com>, <gregory.herrero@intel.com>,
        <yousaf.kaukab@intel.com>, <r.baldyga@samsung.com>,
        <dinguyen@opensource.altera.com>, <cf@rock-chips.com>,
        <hl@rock-chips.com>, <wulf@rock-chips.com>, <yk@rock-chips.com>,
        <huangtao@rock-chips.com>, <walkrain@126.com>, <dianders@chromium.org>,
        <jwerner@chromium.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        <linux-usb@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [RFC PATCH v1] usb: dwc2: reduce dwc2 driver probe time
Message-ID: <20150210144718.GB16711@saruman.tx.rr.com>
Reply-To: <balbi@ti.com>
References: <1423577139-4165-1-git-send-email-lyz@rock-chips.com>
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Hi,

On Tue, Feb 10, 2015 at 10:05:39PM +0800, Yunzhi Li wrote:
> I found that the probe function of dwc2 driver takes much time
> when kernel boot up. There are many long delays in the probe
> function these take almost 1 second.
>=20
> This patch trying to reduce unnecessary delay time.
>=20
> In dwc2_core_reset() I see it use two at least 20ms delays to
> wait AHB idle and core soft reset, but dwc2 data book said that
> dwc2 core soft reset and AHB idle just need a few clocks (I think
> it refers to AHB clock, and AHB clock run at 150MHz in my RK3288
> board), so 20ms is too long, delay 1us for wait AHB idle and soft
> reset is enough.

do you know what's the upper boundary for AHB clock ? How fast can it
be? It's not wise to change timers because "it works on my RK3288
board", you need to guarantee that this won't break anybody else.

The only way to do that is to look at the architecture part of dwc2 and
see if there are any limits to how fast AHB clock can be.

Also, you're not even sure if it refers to AHB clock. Usually, you can
also change which clock source to use, so you need to cope with that as
well.

Please go back to your documentation and figure these out.

Thanks

--=20
balbi

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