Message-ID: <54DBD6D5.9060804@intel.com>
Date: Wed, 11 Feb 2015 14:25:25 -0800
From: "H. Peter Anvin" <h.peter.anvin@intel.com>
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To: Ross Zwisler <ross.zwisler@linux.intel.com>, linux-kernel@vger.kernel.org
CC: Ingo Molnar <mingo@kernel.org>, Thomas Gleixner <tglx@linutronix.de>,
        Borislav Petkov <bp@alien8.de>
Subject: Re: [PATCH v3 2/2] x86: Add support for the clwb instruction
References: <1422377631-8986-1-git-send-email-ross.zwisler@linux.intel.com> <1422377631-8986-3-git-send-email-ross.zwisler@linux.intel.com>
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On 01/27/2015 08:53 AM, Ross Zwisler wrote:
> Add support for the new clwb (cache line write back) instruction.  This
> instruction was announced in the document "Intel Architecture
> Instruction Set Extensions Programming Reference" with reference number
> 319433-022.
> 
> https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf
> 
> The clwb instruction is used to write back the contents of dirtied cache
> lines to memory without evicting the cache lines from the processor's
> cache hierarchy.  This should be used in favor of clflushopt or clflush
> in cases where you require the cache line to be written to memory but
> plan to access the data again in the near future.
> 
> One of the main use cases for this is with persistent memory where clwb
> can be used with pcommit to ensure that data has been accepted to memory
> and is durable on the DIMM.

Acked-by: H. Peter Anvin <hpa@linux.intel.com>


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