Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933531AbbBQJ3t (ORCPT ); Tue, 17 Feb 2015 04:29:49 -0500 Received: from foss.arm.com ([217.140.101.70]:52587 "EHLO usa-sjc-mx-foss1.foss.arm.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754830AbbBQJ3r (ORCPT ); Tue, 17 Feb 2015 04:29:47 -0500 Date: Tue, 17 Feb 2015 09:29:35 +0000 From: Marc Zyngier To: Yun Wu Cc: "tglx@linutronix.de" , "jason@lakedaemon.net" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v2 5/6] irqchip: gicv3-its: add support for power down Message-ID: <20150217092935.1fefcb24@arm.com> In-Reply-To: <1423992723-5028-6-git-send-email-wuyun.wu@huawei.com> References: <1423992723-5028-1-git-send-email-wuyun.wu@huawei.com> <1423992723-5028-6-git-send-email-wuyun.wu@huawei.com> Organization: ARM Ltd X-Mailer: Claws Mail 3.11.1 (GTK+ 2.24.25; arm-unknown-linux-gnueabihf) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1830 Lines: 58 On Sun, 15 Feb 2015 09:32:02 +0000 Yun Wu wrote: > It's unsafe to change the configurations of an activated ITS directly > since this will lead to unpredictable results. This patch guarantees > a safe quiescent status before initializing an ITS. Please change the title of this patch to reflect what it actually does. Nothing here is about powering down anything. > Signed-off-by: Yun Wu > --- > drivers/irqchip/irq-gic-v3-its.c | 32 > ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) > > diff --git a/drivers/irqchip/irq-gic-v3-its.c > b/drivers/irqchip/irq-gic-v3-its.c index 42c03b2..29eb665 100644 > --- a/drivers/irqchip/irq-gic-v3-its.c > +++ b/drivers/irqchip/irq-gic-v3-its.c > @@ -1321,6 +1321,31 @@ static const struct irq_domain_ops > its_domain_ops = { .deactivate = > its_irq_domain_deactivate, }; > > +static int its_check_quiesced(void __iomem *base) > +{ > + u32 count = 1000000; /* 1s */ > + u32 val; > + > + val = readl_relaxed(base + GITS_CTLR); > + if (val & GITS_CTLR_QUIESCENT) > + return 0; > + > + /* Disable the generation of all interrupts to this ITS */ > + val &= ~GITS_CTLR_ENABLE; > + writel_relaxed(val, base + GITS_CTLR); > + > + /* Poll GITS_CTLR and wait until ITS becomes quiescent */ > + while (count--) { > + val = readl_relaxed(base + GITS_CTLR); > + if (val & GITS_CTLR_QUIESCENT) > + return 0; > + cpu_relax(); > + udelay(1); > + } You're now introducing a third variant of a 1s timeout loop. Notice a pattern? Thanks, M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/